Senior RTL Design Engineer, DRAM
7 days ago
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 10 years of experience in micro-architecture and coding in one or more of the following areas: memory compression, interconnects, coherence, cache, DRAM controller, Physical Layer Devices (PHYs).
- Experience with multiple quality checks performed at front-end including Lint, CDC/RDC, Synthesis, LEC, etc.
- Experience with Verilog or System Verilog.
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science.
- 14 years of experience in micro-architecture and coding in one or more of the following areas: memory compression, interconnects, coherence, cache, Dynamic Random Access Memory (DRAM) controller, PHYs.
- Experience with micro architecture design with the knowledge of system design to develop optimized IPs with PPA.
- Experience with chip design flow and with the knowledge of cross-domain involving Design Verification (DV)/Design for testing (DFT)/Physical Design/Software.
- Experience in performance design, Multi power domains with clocking and multiple System on a chip (SoCs) with silicon.
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities- Lead a team of Register-Transfer Level (RTL) engineers with Internet protocol (IP) development to plan tasks, hold code and design reviews, code development of features in the IP.
- Interact with the architecture team and develop implementation (e.g., microarchitecture and coding) strategies to meet quality, schedule and Power Performance Area (PPA) for the IP.
- Work with the cross-functional team of Verification, Design for Test, Physical Design and Software teams to make design decisions and represent project status throughout the development process.
Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.
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