Design Verification Engineer

3 days ago

New Delhi, India Best NanoTech Full time

Position: Formal verification EngineerAbout the RoleExperience with Formal Verification (e.g., sequential equivalence checking, Security Path verification, connectivity, low power and Formal property verification).Responsibilities- Experience with programming languages (e.g., Python/Perl and TCL). - Experience with at least one formal verification tool (e.g., Cadence Jasper, Synopsys VC-Formal). - Expertise in property specification languages (e.g., SVA, PSL). - Proficiency in HDLs such as System Verilog, Verilog or VHDL.Qualifications- Experience-4+ yearsRequired Skills- Formal Verification - Programming languages (Python/Perl and TCL) - Formal verification tools (Cadence Jasper, Synopsys VC-Formal) - Property specification languages (SVA, PSL) - HDLs (System Verilog, Verilog or VHDL)Preferred Skills- None specifiedPay range and compensation package- Location-PuneEqual Opportunity StatementWe are committed to diversity and inclusivity.

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