Senior Digital Design Engineer

3 weeks ago

Bengaluru, Karnataka, India Analog Devices Full time

Job Responsibilities:

  • Designkey digital blocks such as accelerators/ datapath IP in Verilog/ System Verilog with built-in configurability to allow Power/ Performance/ Area tradeoffs
  • Develop strong understanding of heterogenous processor cores & subsystems (A55/ M55/ M4/ U55/ RISC-V/ DSP core, and associated infrastructure such as caches, interconnect fabric, GIC, DMA, MMU, Coresight Debug & Trace, TZC, SMPU, SPU) and their integration requirements
  • Package Digital IP for seamless integration into design flow at different stages – RTL/ constraints/ CDC waivers, timing wavers, DFT DRCs and waivers, software programming sequence etc
  • Consolidate & curate digital IP for SPI/ I2C/ UART/ JTAG and other slow serial interfaces & peripherals
  • Evaluate 3rd party IPs on Power/ Performance/ Area (PPA) and other key qualitative aspects such as design quality, Design For Testability, robustness of Design Verification (DV) practice, ease of integration and make recommendations
  • Build expertise on complex interfaces, peripherals & protocols such as DDR, Ethernet, eMMC/ SD, MIPI, Display Port, HDMI, PCIe, high speed D2D
  • Develop and maintain catalog of digital IPs to enable ease of information sharing to customers across different BUs
  • Develop User Guides for RTL Integration, Synthesis, DFT, PnR, Programming Sequence, characterization etc
  • Establish evaluation flows for home-grown & 3rd party IPs for consistent benchmarking of evaluation

Position Requirements:

  • Minimum B.E. / B.Tech degree in Electrical/Electronics/Computer science
  • 4 - 8 years of digital logic design and hands-on RTL coding experience using Verilog and SystemVerilog
  • Strong understanding of control path and data-path digital design concepts with an eye for realizing correct by construction solutions
  • Experience with specifying Design Verification (DV) requirements such as test plans, coverage metrics, and evaluate DV quality so as to realize robust design quality
  • Knowledge of Lint, CDC, formal equivalence, DFT concepts, power analysis
  • Experience with developing timing constraints and ability to carry out logic synthesis and Static timing analysis
  • Good interpersonal, teamwork and communication skills to logically & effectively drive discussions with teams spread geographically
  • Understanding of standard on-chip interfaces such as APB/AHB/AXI/ Stream protocols is a strong plus
  • Knowledge of Processor/SoC architecture and/or DSP fundamentals is a strong plus
  • Experience with end-to-end ASIC/ SoC product development & productization is very desirable

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