Staff/Sr. Staff System IP Design Verification Engineer
5 days ago
We're looking for a passionate and hands-on RISC-V System IP DV Engineer to architect, develop, and evolve world-class verification infrastructure for System IPs (interrupt controllers, IOMMU, power management, DFD etc) that will be integrated in high-performance RISC-V CPU clusters. If building from scratch, innovating on methodology, and collaborating with top-tier CPU designers excites you — read on.
This role is hybrid, based out of Bangalore.
We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting
Who You Are
- You bring domain understanding of memory management at core/system level, concepts like virtual/physical memory, page tables etc
- You thrive in building robust verification environments using SystemVerilog and UVM, and optionally C++, and can define and drive verification plans independently.
- You have a strong grasp of stimulus planning, checker development, debug techniques, and coverage closure for verifying complex hardware subsystems.
- You're comfortable working on features that span multiple IPs and can devise plans to verify them at IP, subsystem and fullchip levels.
What We Need
- A Bachelor's or Master's degree in Electrical Engineering, Computer Science, or a related field.
- 7 - 15 Years of Strong experience with System Verilog and UVM-based verification.
- Proven ability to drive IP level and subsystem level DV projects.
- Familiarity with core MMU or SMMU/IOMMU, bus protocols like AXI.
What You Will Learn
- Owning a large scope with a small focused team.
- How to structure and deliver a configurable IP to SoCs with seamless integration in mind.
- How IOMMU can be integrated in a SoC, collaborating closely with RTL designers, architects etc.
- Building reusable verification components, coverage models, and checkers that scale across multiple abstraction layers.
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