Incise Infotech

Immediate Joiners Preferred

About the Role :

Incise Infotech Limited is expanding its VLSI Design team and is looking for skilled Static Timing Analysis (STA) Engineers to contribute to high-performance chip design projects.

This role is ideal for engineers passionate about full-chip timing closure, constraint development, and timing verification in advanced technology nodes.

Key Responsibilities :

- Perform Static Timing Analysis at both block and full-chip levels using industry-standard tools such as PrimeTime or Tempus

- Analyze and debug setup, hold, transition, and other timing violations

- Work closely with RTL, Synthesis, and Physical Design (PD) teams to drive timing closure

- Develop, validate, and manage SDC constraints for various design stages

- Ensure timing sign-off readiness by generating and reviewing timing reports

- Innovate and automate STA flows for improving efficiency and quality of results

- Collaborate with design teams to support tape-out schedules and quality metrics

- Perform PPA (Power, Performance, Area) analysis and support ECO timing closure

- Support multiple projects by providing STA inputs during design reviews

Required Skillsets

- Hands-on experience in STA tools like PrimeTime, Tempus, etc.

- Strong understanding of timing concepts, clock domains, and signal integrity

- Expertise in writing and debugging SDC constraints

- Solid knowledge of CMOS, VLSI design flows, and timing closure methodologies

- Proficient in TCL scripting and automation of STA reports and flows

- Familiarity with synthesis, floorplanning, and physical design interactions

- Experience with advanced technology nodes (e.g., 7nm, 16nm, 28nm) is a plus

- Good communication and problem-solving skills

- Ability to work independently and collaboratively in a fast-paced environment