
ASIC Test Engineer
5 days ago
#Urgent_Opening_for_Canvendor
#Hiring: ASIC Test Engineer (5-15 Years Experience) | Bangalore | Hyderabad| Pune| Immediate Joiners Preferred
Job Title: ASIC Test Engineer
Location: Bangalore/ Hyderabad/ Pune
Experience Level: 5-15 Years
Notice Period : Immediate to 15 Days
Key Requirements:
Test development on an Advantest V93000 platform using SmarTest 8 for the following blocks/interfaces and functionality:
• ADC/DAC
❖ Internal loopback
❖ SCAN (stuck-at and transition delay
❖ Pre & Post-trim including temperature sensors
❖ IO DC parametric tests
❖ Process monitor / ring oscillator tests
• SERDES (CPRI, PCIE)
❖ Internal & external loopback – external loopback at package only
❖ IO DC parametrics tests
❖ Register/PLL lock checks using either APB (Advanced Peripheral Bus) or iJTAG for
access.
❖ Stuck-at and Transition Delay SCAN. Fault coverage levels TBD.
❖ IDD (Current into VDD supply pin) – if separate power supply available.
• ATPG (Automatic Test Pattern Generation)
❖ Stuck-at
❖ Transition Delay
❖ Cell-aware / Small Delay Defect(?)
❖ Memory Built-in Self-Test (MBIST) & BISR (Built-in Self Repair)
❖ Logic Built-in Self-Test (LBIST)
• Boundary Scan (BSDL, Boundary Scan Description Language)) - IEEE1149.1 &
IEEE1149.6
• Programming LTU chip
• Process Monitors (ProteanTec / Synopsys)
• High Voltage Stress Testing – Cyclic Alternating Voltage Stress per TSMC
• Very Low Voltage (VLV) Testing
• IO Parametric Tests – leakage, Vix, Vox
• IDD – quiescent/gross, functional/dynamic, sleep
• Top Level Verification (TLV) functional patterns, e.g., Path Delay, if any
• Production Test & Yield Ramp – optimize test time, support binning, yield analysis.
• Failure Analysis Support – debug routines (shmoo, scan diagnosis), provide reports.
If interested kindly share your updated CV to irfanai@canvendor.com
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