Senior Design Verification Engineer
3 weeks ago
Dear reader, We are from TA team hiring for VLSI skills. Our team is looking to expand our DV team. Please feel free to look us up at
- We are looking for DV engineers who have strong experience to SV/UVM primarly .
- Having PCIE protocol / Knowledge would be a added advanatage.
- PCIE Physical & Data Link Layer protocol coverage model development & coverage analysis, regression failure triage & testbench bug fixes.
- Bringup & debug of xprop, 0-delay gatesims, power sims.
- May also involve integration qualification of subunit design/models, VIP in unit DV environment.
Regards,
Sreenath Vijayan
sreenath.vijayan@ltts.com
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