Analog Layout Engineer

2 weeks ago

New Delhi, India ACL Digital Full time

Analog Layout EngineerRequired Qualifications: Bachelor’s or Master’s degreeinElectrical Engineering ,Computer Engineering , or a related field. 4+ years of experienceinanalog layout designwith a focus onTSMC 7nm ,5nm , and3nmprocess technologies. Proficiency withCadence Virtuoso ,Mentor Graphics ,Synopsys IC Compiler , or equivalent analog layout tools. Hands-on experience withTSMC PDKsand process technologies for7nm ,5nm , and3nmnodes. Strong knowledge ofanalog circuit design principles , includingtransistor-level design ,biasing ,signal integrity , andnoise analysis . Extensive experience withDRC ,LVS ,parasitic extraction , and layout verification using tools such asCalibreandICValidator . In-depth knowledge ofFinFET ,SOI , and other advanced semiconductor process technologies at sub-7nm nodes. Ability to optimize analog layouts forPPA (performance, power, area) . Experience withlow-power design techniquesinadvanced process nodes . Familiarity withhigh-performance analogdesigns and layouts in7nm ,5nm , and3nmtechnologies. Strong problem-solving skills and ability to troubleshoot and resolve layout issues.Preferred Qualifications: Experience withmixed-signal layouts(analog and digital) forfull-chip designs . Familiarity withRFlayout techniques for high-frequency analog circuits. Experience in working withmultiple layout design environments(e.g.,Virtuoso ,IC Studio ,Synopsys Custom Compiler ). Knowledge ofelectromagnetic interference (EMI) ,signal integrity , andhigh-speed layout techniquesin advanced nodes. Exposure tofull-custom layouttechniques for complexanalog IC designs . Understanding ofadvanced packaging technologiesand their impact on analog layout design. Experience withstatistical analysis toolsfor yield and design optimization.Location: Bangalore Experience: 4 to 8 Years

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