Staff Engineer

4 weeks ago


Coimbatore, India Mulya Technologies Full time

Staff Engineer - STA/Synthesis

Top10 Semiconductor Organization in the World

Hyderabad

We are a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

Staff Engineer - STA/Synthesis


Unique Opportunities


  • Collaborate closely with design and verification team members spread across the globe, many of whom have decades of experience in memory design.
  • Work and own STA and allied Methodologies for HBM designs

Responsibilities


  • Build function and timing models for standardized and customized logic design.
  • Perform Static Timing Analysis on the memory control logic design with industry lead EDA tools
  • Deploy the RTL-IP with the standardized flow and continue improving the flow for high quality
  • Supporting the RTL-IP user for layout process including floor-planning, placement, and routing
  • Perform verification processes with modeling and simulation using industry standard simulators

Core Requirements


  • Good communication skills and ability to work well in a team
  • Guide new team members and energetic engineers in the team
  • Analytical capability for complex CMOS and/or gate level circuit designs
  • Proficient with either STA tools and methodologies , and generating timing constraints
  • Good understanding on timing/area/power/complexitytradeoffs on complex interface design
  • Familiar with IP level verification and strong RTL debugging capabilities
  • Maintain technical expertise and provide training
  • Contribute to cross group communication to work towards standardization and group success
  • Proactively solicit input from Standards, CAD, modeling, and verification groups to ensure the design quality
  • Drive innovation into the future Memory generation with dynamic work environment Successful candidates for this position will have:
  • Rich experience in STA and making timing constrains based on Primetime or it’s counterparts

Qualifications & Skills


  • Experience in frontend implementation tasks such as synthesis and logic equivalence
  • Experience in large scale mix signal circuitry design including logic implementation/verification, timing analysis/optimization an advantage
  • Experience in ASIC backend flow with parasitic extraction and timing closure is a plus
  • Experience in liberty/Verilog model characterization is a plus
  • Experience in leading a team is a plus
  • Excellent problem-solving and analytical skills



Education


Bachelors or Post Graduate Degree in Electronics Engineering or related engineering field required


Contact:

Uday

Mulya Technologies

muday_bhaskar@yahoo.com



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