Senior ASIC/SoC Engineer/Lead
3 weeks ago
Responsibilities :
- SoC/IP Design: Develop and implement cutting-edge SoC and IP designs, ensuring high performance and reliability.
- RTL Design: Expertise in IP design, subsystem/cluster, and SoC level integration using Verilog/System Verilog.
- RTL Quality Checks: Perform rigorous RTL quality checks including linting and CDC to ensure design robustness and reliability.
- Synthesis and Low Power: Knowledge of synthesis and low power techniques to optimize design performance and power consumption.
- AMBA Bus Protocols: Good understanding of AMBA bus protocols such as AXI, AHB, ATB, and APB.
- Timing Concepts: Solid understanding of timing concepts to ensure design meets performance requirements.
- Interface Protocols: Knowledge of one or more interface protocols including PCIe, DDR, Ethernet, I2C, UART, and SPI.
- Tool Proficiency: Expertise in setting up and using design tools such as Spyglass Lint/CDC, Synopsys DC, and Verdi/Xcellium.
- Scripting: Understanding of scripting languages like Makeflow, Perl, shell, and Python to automate design tasks and flows.
- Processor Architecture: Understanding of processor architecture and/or ARM debug architecture is a plus.
- Issue Debugging: Ability to help and debug issues across multiple subsystems to ensure smooth design execution.
- Design Documentation: Create and review design documents for multiple subsystems to ensure clarity and completeness.
- Cross-Functional Support: Collaborate with physical design, verification, DFT, and software teams to address design queries and reviews.
Qualifications :
- Bachelor's/Master's degree in Electrical/Computer Engineering or related field.
- Minimum of 5 years of experience in ASIC/SoC RTL design and integration.
- Strong proficiency in Verilog/System Verilog.
- Experience with AMBA bus protocols and interface protocols.
- Familiarity with design and verification tools.
- Excellent problem-solving and debugging skills.
- Strong communication and collaboration skills.
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