Senior DV Engineer
2 days ago
LTTS is hiring for Design Verification Engineers with 5+ Years of experience.Job Location : Bangalore, IndiaDetailed JD is as below ::Job Description DV Positions:Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-stem/SoC level verificationDevelop functional tests based on verification test planDrive Design Verification to closure based on defined verification metrics on test plan, functional and code coverageDebug, root-cause and resolve functional failures in the design, partnering with the Design teamQualifications and Skills for DV Positions:Bachelor's or Masters degree in Computer Science, Electronics Engineering or equivalent practical experience5 + of hands-on experience in StemVerilog/UVM methodology and/or C/C++ based verification5+ experience in IP/sub-stem and/or SoC level verification based on StemVerilog UVM/OVM based methodologiesExperience in development of UVM based verification environments from scratchExperience in architecting and implementing Design Verification infrastructure and executing the full verification cycleExperience with verification of ARM/RISC-V based CPU sub-stems or SoCsExperience with IP or integration verification along with expertise of protocols like AMBA, PCIe, DDR, USB, EthernetExperience in E tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environmentsExperience with revision control stems like Mercurial(Hg), Git or SVN
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Staff DV Methodology Engineer
3 weeks ago
Delhi, India Mulya Technologies Full timeStaff DV Methodology EngineerWe are a US based Stealth mode Start-uplocation: Hyderabad / Bangalore / Remote ( any where in India )We unify the processes used in Semiconductor and Hardware Systems design - thus reducing bugs, improving efficiency and productivityOur breakthrough technology has drawn investment from Silicon Valley’s boldest VCs and...
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Staff DV Methodology Engineer
3 weeks ago
Delhi, India Mulya Technologies Full timeStaff DV Methodology EngineerWe are a US based Stealth mode Start-uplocation: Hyderabad / Bangalore / Remote ( any where in India )We unify the processes used in Semiconductor and Hardware Systems design - thus reducing bugs, improving efficiency and productivityOur breakthrough technology has drawn investment from Silicon Valley’s boldest VCs and...
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Senior DV Engineers
8 hours ago
New Delhi, India L&T Technology Services Full timeLTTS is looking for DV engineers with 7+ years of experience for lead role...detailed JD is below mentioned.8/10+ of hands-on experience in StemVerilog/UVM methodology and/or C/C++ based verification8/ 10+ experience in IP/sub-stem and/or SoC level verification based on StemVerilog UVM/OVM based methodologiesExperience in development of UVM based...
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Staff Gen AI DV Methodology Engineer
3 weeks ago
Delhi, India Mulya Technologies Full timeStaff Gen AI DV Methodology EngineerWe are a US based Stealth mode Start-uplocation: Hyderabad / Bangalore / Remote ( any where in India )We unify the processes used in Semiconductor and Hardware Systems design - thus reducing bugs, improving efficiency and productivityOur breakthrough technology has drawn investment from Silicon Valley’s boldest VCs and...
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Staff Gen AI DV Methodology Engineer
3 weeks ago
Delhi, India Mulya Technologies Full timeStaff Gen AI DV Methodology EngineerWe are a US based Stealth mode Start-uplocation: Hyderabad / Bangalore / Remote ( any where in India )We unify the processes used in Semiconductor and Hardware Systems design - thus reducing bugs, improving efficiency and productivityOur breakthrough technology has drawn investment from Silicon Valley’s boldest VCs and...
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New Delhi, India BITSILICA Full timeSkill: Senior DV Engineer Exp: 5-10 Years Location: Singapore Notice: Immediate - 30 daysJD: Test bench development and debug Strong Expertise in Digital, Verilog & SV. UVM/C based test case development and debug. Power aware test case development and debug External/Internal VIP based test development and debug. Mixed-signal block modelling and RNM based...
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Senior Design Verification Engineer SIngapore
11 hours ago
New Delhi, India BITSILICA Full timeSkill: Senior DV EngineerExp: 5-10 YearsLocation: SingaporeNotice: Immediate - 30 daysJD:- Test bench development and debug - Strong Expertise in Digital, Verilog & SV. - UVM/C based test case development and debug. - Power aware test case development and debug - External/Internal VIP based test development and debug. - Mixed-signal block modelling and RNM...
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Design Verification Engineer
2 days ago
New Delhi, India Canvendor Full time#Urgent_Opening_for_Canvendor#Hiring: DV Engineer (4-10 Years Experience) |Bangalore| Immediate Joiners PreferredLocation: Chennai, IndiaExperience: 4-10 YearsNotice period: Immediate to 30daysMandatory: IP/SS verification of complex blocks (CPU SS), Fabric/NOC/Interconnect blocks, AMBA, SV, UVM#Key_Requirements:IP Verification-Experience in executing IP/SS...
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RTL Design Engineer
2 days ago
New Delhi, India ACL Digital Full timeJob Title: RTL Design Engineers Exp Level: 2-3 yrs Loctaion: HyderabadJob Description:Seeking a motivatedRTL Design Engineerto develop, integrate, and verify digital logic usingVerilog/SystemVerilog . Responsibilities includeASIC/SoC IP integration , linting, synthesis, and working closely with verification teams. Requiresstrong fundamentals in digital...
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Senior/ Lead Analog Design
4 days ago
New Delhi, India Texas Instruments Full timePosition: Senior Analog Designer/LeadAbout Us:High Speed Amplifiers (HSAMP) is a product line under Linear Amplifier BU working on different high-speed (50MHz – few GHz), high-performance product families (VFA, CFA, Buffers, FDA, TIA, Log-amp, LiDAR TX/RX) using CMOS and Bipolar technologies. The products are both catalog & application specific,...
