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Principal DFT Engineer

1 month ago

Cochin, Kerala, India Mulya Technologies Full time
Principal DFT Engineer
Bangalore (Hybrid ) / Hyderabad (Hybrid ) / India-WFH(Remote )
Principal DFT Engineer
Full Time \ Experienced
Summary
Join an ambitious, experienced team of silicon and distributed systems experts as a Design For Test engineer. You have the opportunity to build a groundbreaking new category of product that revolutionizes the performance and scalability of next-generation distributed computing systems, and to help solve key infrastructure challenges facing our customers.
We are looking for talented, motivated candidates with experience building and deploying DFT flows for large-scale networking and computing chips, and who are looking to grow in a fast paced, dynamic startup environment.
Roles & Responsibilities
As a member of our team, you will work with multi-functional teams, implementing state-of-the-art designs in test access mechanisms, IO BIST, memory BIST and scan compression.
You will work with 3rd party IP vendors to integrate Memory BIST, scan, PHY I/O BIST, and other DFT logic into a streaming scan fabric with a sequential scan compressor/decompressor
You will work with DFT Solutions Vendors to port those patterns at the top-level, to implement Memory BIST interface in high performance processor IP, and to implement high-speed I/O for the logic scan test
You will work with Physical Designers to validate the DFT timing constraints
You will work with RTL Designers to verify test design rules
You will work with Test Engineers to bring up the patterns on the ATE Automated Test Equipment
You will help develop and deploy DFT methodologies for our next generation products.
Key Qualifications
MSEE or equivalent experience
7+ years of experience in DFT or related domains
You will have a solid knowledge and expertise in defining scan test plans, BIST including memories and IOs, fault modeling, ATPG and fault simulation
Possess excellent analytical skills in verification and validation of test patterns and logic on complex and multi-million gate designs using vendor tools
Have good exposure to cross functional areas including RTL & clocks design, STA, place-n-route and power, to ensure we are making the right trade-offs
Experience in Silicon debug and bring-up on the ATE with an understanding of pattern formats, failure processing, and test program development
Strong programming and scripting skills in Perl, Python or Tcl desired
Exceptional written and oral and interpersonal skills with the curiosity to work on rare challenges
Contact:
Uday
Mulya Technologies
"Mining The Knowledge Community"