Lead Design Engineer

Lead Design Engineer As anRTL Design Lead , you will play a critical role in leading the RTL design and verification process for complexdigital designs . You will manage a team ofRTL engineers , collaborate with cross-functional teams, and ensure the successful implementation of high-performance, low-power designs. The ideal candidate should have a strong technical background inRTL design , experience indigital design flow , and the ability to lead a team towards the successful execution of complex projects.Key Responsibilities: RTL Architecture and Design:Lead the RTL design of complex digital systems, includingmicroprocessors ,ASICs ,FPGA designs , andsystem-on-chip (SoC)components. Team Leadership:Manage and mentor a team ofRTL design engineers , providing technical guidance, training, and fostering a collaborative team environment. Design Specifications:Work closely withsystem architectsandhardware engineersto define design specifications, ensuring the implementation meets performance, area, and power requirements. RTL Coding:Write and reviewhigh-quality RTL codeinVerilog ,SystemVerilog , orVHDL , focusing on scalability, reusability, and modularity. Design Validation:Lead the development of testbenches and collaborate with verification teams to ensure the design is thoroughly verified usingsimulation ,formal verification , andcoverage analysis . Timing and Performance Optimization:Drive performance and timing closure by working with design and implementation teams to address critical paths and optimize the design forlow power ,high speed , andminimal area . Integration:Lead the integration of RTL design blocks into larger systems, ensuring smooth handoffs between various teams, includingdigital, analog , andsoftwareteams. Mentorship and Collaboration:Provide mentorship to junior engineers and collaborate with cross-functional teams, includingverification ,software , andphysical designteams to ensure the design meets all system requirements. Documentation and Reporting:Ensure the proper documentation of design flows, methodology, and processes, including regular design reviews and progress reports to management. Continuous Improvement:Drive continuous improvement in RTL design methodologies, best practices, and tools. Stay up to date with the latest trends and technologies inRTL designanddigital systems .Required Qualifications: Bachelor’s or Master’s degreeinElectrical Engineering ,Computer Engineering , or a related field. 7+ years of experienceinRTL designfor complexdigital systems , with at least3+ years of leadership experiencein managing teams and projects. Expertise inVerilog ,SystemVerilog , orVHDLfor RTL coding, with a strong understanding ofdigital design principles . Proven experience in designing and verifying large-scaleSoC ,ASIC , orFPGA designs . Strong understanding ofdigital design flow , includingsynthesis ,place-and-route ,timing analysis , andpower optimization . Experience withsimulation and verification methodologies , includingUVM ,SV-based testbenches , andcoverage-driven verification . Proficient in usingEDA toolssuch asCadence ,Synopsys ,Mentor Graphics , or other RTL design and verification tools. Strong knowledge oftiming analysis ,static timing analysis (STA) , andpower optimization techniques . Excellent problem-solving and debugging skills, with experience in addressing complex design issues. Strongcommunication skillswith the ability to articulate technical ideas clearly and effectively to both technical and non-technical stakeholders.Experience: 7 to 12 Years Location: Bangalore