SRAM Memory Design
4 weeks ago
Job Function:
Samsung Foundry's SRAM Design Group in Bangalore develops various types of SRAMs, register files, and ROMs in advanced technology nodes like 4nm, 2nm, and beyond.
The team is responsible for delivering highly competitive memories for SAMSUNG Foundry customers.
This role provides a unique opportunity for individuals who are willing to innovate and solve the most challenging problems in circuit design.
Samsung Foundry, a pioneer in new device technology, creates ample opportunities for circuit designers to innovate and design highly competitive IPs.
Roles & Responsibilities:- Design Highly Competitive Circuits: Meet performance/power specifications requested by customers
- Lead a Team: Guide and lead a group of engineers to deliver the SRAM IP in given timelines
- Analyze Circuits: Identify potential robustness gaps and find solutions to improve robustness of the design
- Owning Responsibility: From SPEC to GDS and DK delivery
- Review Reports: Review circuits, robustness reports, and identify potential robustness issues
- Review layouts and suggest improvement areas to achieve competitive PPA
- PPA Trade-offs: Understanding of SRAM PPA trade-offs and identify right techniques to meet SPECS
- Communication: Must be able to communicate effectively across different teams
- Experience: 11-19 years in Memory design or related field
- Degree: Master/Bachelor in Electronics
- Fundamentals: Understanding of RC network and finfet fundamentals
- SRAM/ROM Development: Custom or Compiler SRAM/ROM development experience
- Process Variability: Fundamentals of process variability and its effect on memory design
- SQM Knowledge: Thorough understanding of SRAM bit cell and its characteristics (Read current, Standby current, data retention, SNM)
- Circuit Design Fundamentals: Strong understanding of circuit design fundamentals
- Critical Path Modeling: Critical path modeling concept, various type of models (RC, C, Pai, ladder)
- Semiconductor Physics: Good knowledge of semiconductor physics (finfet function, parasitic etc)
- LLE Effects: Analyzing layout and understanding of LLE effects
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