PCIe Protocol Verification Engineer
3 days ago
Project Description:We are passionate about transforming lives through cutting-edge technology, enriching industries, communities, and the world. Our mission is to create exceptional products that drive next-generation computing experiences, serving as the foundation for data centers, artificial intelligence, PCs, gaming, and embedded systems.At the core of our mission lies a culture of innovation. We challenge boundaries to solve some of the world's most critical problems. We are committed to execution excellence, fostering a culture of openness, humility, collaboration, and inclusivity, valuing diverse perspectives along the way.Responsibilities:- Perform functional and compliance verification of PCIe-based SystemC IPs and subsystems. - Integrate SystemC PCIe IP/Subsystem in Avery PCIe VIPs and utilize for protocol-level verification. - Debug complex issues across transaction, data link, and physical layers of PCIe. - Analyze and interpret PCIe specifications for test planning and coverage. - Work closely with design, architecture, and validation teams to ensure feature completeness and spec compliance. - Generate and review verification plans, test reports, and coverage metrics.Mandatory Skills Description:- 5+ years of experience. - Strong hands-on experience with Avery PCIe VIP (integration, debug, customization). - In-depth knowledge of PCIe protocol (Gen4/Gen5 or higher). - Solid experience in SystemVerilog / UVM methodology. - Strong debug and problem-solving skills using simulators like Questa, VCS, or Xcelium. - Familiarity with coverage-driven verification and constraint random testing. - Good understanding of verification flow, regression setup, and scripting (Python/Perl/Shell). - Excellent communication skills and ability to work independently in a fast-paced environment.Nice-to-Have Skills Description:- B.E/M.E/M.Tech or B.S/M.S in EE/CE
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PCIe Protocol Verification Engineer
5 days ago
Delhi, India Luxoft Full timeWhy Luxoft?Work–Life Balancewith flexible work hours (agreed with your manager).Multiple working modes:Physical, Flexible, Virtual, and Onsite.Cab facilitiesfor employees.Free gym access+ free sports equipment and sports zones.Corporate sports eventsand well-being programs.LuxGood activities:motivational talks, games, wellness content, community...
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Design Verification Engineer
1 week ago
New Delhi, India Proxelera Full timeKey Responsibilities & Skills:* Perform functional and compliance verification of PCIe-based IPs and subsystems.* Integrate and debug using Avery PCIe VIPs.* Deep understanding of PCIe Gen4/Gen5 protocols.* Expertise in SystemVerilog and UVM methodology.* Strong debug skills with VCS, Questa, or Xcelium.* Experience in coverage-driven and constraint-random...
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DDR / PCIe / NVMe / UCIe - Verification Engineer
2 weeks ago
New Delhi, India ACL Digital Full timeDesign Verification Engineer - Senior / Lead / Sr. LeadLocation: Bangalore / HyderabadExperience: 4 to 10 YearsRequired Qualifications:- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. - 4+ years of hands-on experience in design verification of high-speed interfaces such as DDR, PCIe, UCIe, or NVMe. -...
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Design Verification Engineer
1 week ago
Delhi, India Proxelera Full timeKey Responsibilities & Skills:* Perform functional and compliance verification of PCIe-based IPs and subsystems.* Integrate and debug using Avery PCIe VIPs.* Deep understanding of PCIe Gen4/Gen5 protocols.* Expertise in SystemVerilog and UVM methodology.* Strong debug skills with VCS, Questa, or Xcelium.* Experience in coverage-driven and constraint-random...
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Senior Design Verification Architect
2 weeks ago
New Delhi, India Eximietas Design Full timeHi All, Eximietas Design Hiring Senior SoC Design Verification Architects / Sr. Manager. Experience: 10+ Years. Location: Bengaluru or Visakhapatnam or San Jose, Bay Area, & Austin, USA. Anyone with a Valid H1B or Already in US.Job Description: #Lead SoC Design Verification efforts for complex projects, ensuring successful execution of verification plans....
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Senior Design Verification Engineer
2 weeks ago
New Delhi, India BITSILICA Full timeBITSILICA is Hiring – PCIe Verification ExpertsWe’re looking for skilled PCIe Verification Engineers with 4+ years of experience on Pcie to join our growing team in #HyderabadWhat We’re Looking For:Hands-on experience in PCIe protocol verification using #SystemVerilog / #UVMStrong understanding of PCIeGen3 specificationsExperience with simulation,...
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Functional Verification Engineer
3 days ago
New Delhi, India ACL Digital Full timeLead Functional Verification EngineerExperience: 6+ YearsLocation: BangaloreJob Description:- Lead verification activities for complex CPU cores, memory subsystems, and high-speed PCIe IPs. - Define verification strategy, test plan, and coverage goals based on architecture and spec reviews. - Build and maintain advanced UVM-based testbenches for block and...
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DV- PCIE Verification Engineer
3 days ago
New Delhi, India ACL Digital Full timeJob Location: Bangalore/ Hyderabad Notice Period: 15 days to 30 Days Minimum: 4 Years Key Responsibilities: Developing test plans Coding and bring up of asm, c++ tests UVM test bench components coding and maintaining Debugging regression fails Protocol: DDR,PCIE,USB,MIPI, PCIEPreferred Experience: Should have worked on Processor based System or Sub-system...
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New Delhi, India ACL Digital Full timeDesign Verification Engineer - Senior / Lead / Sr. Lead Location: Bangalore / Hyderabad Experience: 4 to 10 YearsRequired Qualifications: Bachelor’s or Master’s degreeinElectrical Engineering,Computer Engineering, or a related field. 4+ years of hands-on experienceindesign verificationof high-speed interfaces such asDDR, PCIe, UCIe, or NVMe. Expertise...
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Senior Design Verification Engineer
3 weeks ago
Delhi, India BITSILICA Full timeBITSILICA is Hiring – PCIe Verification Experts We’re looking for skilled PCIe Verification Engineers with 4+ years of experience on Pcie to join our growing team in #Hyderabad What We’re Looking For: Hands-on experience in PCIe protocol verification using #SystemVerilog / #UVM Strong understanding of PCIeGen3 specifications Experience with simulation...
