Senior Principal Digital Design Engg
3 days ago
Responsibilities :
OnSemi is seeking a Sr. Principal Digital design, NEW PRODUCT DEVELOPMENT, Power Management, to join our growing team in Bengaluru, India. This group is responsible for development of Power management products including DC-DC PMIC/POL, Multiphase controllers, Dr. MOS, AC-DC converters, LED drivers, SiC drivers, Switches and efuses for consumer, industrial and automotive applications. In this role, you will focus on the following:
Work with different product lines for RTL implementation of power convertor controller design like multiphase controller loop / AC-DC control loops, power driver digital controls for LED/SiC FET application, peripherals like I2C, SPI, LIN, CAN protocols The candidate will work on digital design architecture, digital RTL, low power design, synthesis and timing analysis, Physical Design interface for the power management chips using state of the art RTL2GDS flows for IPs and full chip design The candidate will be able to work as part of a large and focused team of engineers and will be able to collaborate successfully as needed with design architects, digital verification, project management, and digital and analog design teams in multiple worldwide geographies Implement micro-architecture to RTL implementation with the refining of features requirements throughout the design process Support the bring-up of various features at a system level in various pre-silicon platforms like SOCV, Emulation, FPGA. Own technical outcome of design, verification, implementation, and execution of Power Management ICs with complexities that can span from simple regulators to complex designs, control loops, and digital interfaces Understand project goals, execute with realistic schedule, report status of progress and understand clarity of project details and milestones Lead and support Customer issues, Production issues, FW and System development, Failure Analysis Support post-silicon validation activities for your designs#LI-RG1
Qualifications:
BS in Electrical Engineering or related + 12 years of experience, or MS + 10 years of experience in working and leading Digital Design, Architecture and ASIC/Mixed signal chip developments The ideal candidate should have thorough understanding of the end-to-end digital design flow in order to accurately and efficiently collaborate with all members of the technical staff, both analog and digital, regarding overall project development progress and status Solid understanding of RTL design, CDC, ASIC synthesis, timing analysis and CDC, P&R, UPF and system Verilog (assertion) Solid understanding of Verilog, TCL and Perl/Python/XML programming languages-
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