STA engineers
2 months ago
STA Engineers:
Location: Bangalore/Hyderabad/Pune/Noida
Responsibilities
- ·Ability to work with RTL design team to identify the must changes in RTL to coverage the timing and work with PD teams to analyze the post route timing & support the final timing closure.
- Drive the sign-off timing convergence for high performance designs.
- Work closely with block owners throughout the project for sign-off timing convergence.
· Timing analysis, validation and debug across multiple PVT conditions using PT/Tempus
- Run Primetime and/or Tempus for STA flow optimization and Spice to STA correlation.
- Evaluate multiple timing methodologies/tools on different designs and technology nodes.
Minimum Qualifications:
- Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
Preferred Qualification/Skills
- Experience in timing analysis/debug and driving the timing convergence for complex blocks & release the netlists to PD team
- Strong expertise in STA timing analysis basics, AOCV/POCV concepts, CTS, defining and managing timing constraints, Latch transparency handling, 0-cycle, multi-cycle path handling
- Hands-on experience with STA tools - Prime-time/ Tempus
- Have experience in driving timing convergence at Chip-level and Hard-Macro level
- In-depth knowledge cross-talk noise, Signal Integrity, Layout Parasitic Extraction, feed through handling,
· Hands on experience on constraint development for synthesis from scratch is a plus
- Knowledge of ASIC back-end design flows and methods and tools (ICC2, Innovus)
- Knowledge of Spice simulation Hspice/FineSim, Monte Carlo. Silicon to spice model correlation is a plus
- Proficient is scripting languages – TCL, Perl, Awk
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