Power Management Design Engineer

5 hours ago


New Delhi, India Best NanoTech Full time

Job Description:We are seeking a highly experienced Power-Management & PLL Circuit Engineer to lead the design and development of advanced power-management circuits and PLL IPs for complex SoCs. This is a senior, hands-on technical role requiring deep analog/mixed-signal expertise.Key Responsibilities Lead the design ofpower-management circuits : LDOs (ultra-low noise, capless, fast-transient), DC-DC converters (PWM/PFM), and voltage regulators. Design and implementhigh-performance PLL circuitsfor frequency synthesis and clock generation. Performadvanced transistor-level simulations , modeling, and analysis to ensure performance and robustness. Work closely withlayout teamsto guide floorplanning, layout practices, and physical design reviews. Drivelab bring-up, silicon debug, and characterizationof PMIC and PLL circuits. Definespecifications and system-level requirementsin collaboration with architecture and SoC teams. Mentor and guide junior engineers in circuit design, simulation, and lab methodologies.Required Qualifications (Essential) Bachelor’s or Master’s degree inElectrical Engineeringor related field. 10+ years of hands-on experiencein power-management and PLL circuit design. Strong foundation inanalog/mixed-signal fundamentalsand feedback loop stability. Expertise in designing LDOs, DC-DC converters, voltage regulators, and PLL building blocks. Proficiency with industry-standard simulation tools ( Cadence Virtuoso, Spectre, ADE , etc.). Strong experience withlab testing , silicon validation, and characterization equipment.


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