Memory Layout Engineer

4 weeks ago


Bengaluru, Karnataka, India Tech Mahindra Full time

We're looking for talented Memory Layout Engineers with 3 to 7 years of experience to join our dynamic team. If you have a strong background in physical design, memory compilers, and layout optimization, we'd love to connect

Job Description:

  • Hands on experience on different Memory Leaf cells like IO/xdec/predec layout design, from scratch including memory top level integration.
  • Sound knowledge & hands on experience in Finfet technology, preferably N4/N3/N2
  • Good knowledge on different types of memory architectures.
  • Good knowledge in optimized layout design for better performance.
  • Proficient in physical verification flow & debug, like DRC, LVS, ERC, Boundary conditions.
  • Proficient in Cadence Virtuoso layout editor and Calibre physical verification flow

Interested or know someone who fits the bill? Drop your resume at sm00822649@techmahindra.com.



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