Standard Cell Design Engineer

3 days ago

Patna, India M31 Technology Full time

Standard Cell Design EngineerCompany Overview:M31 Technology Corporationis a leading provider of silicon intellectual property (IP) solutions, headquartered in Hsinchu, Taiwan. With extensive expertise in IP development, IC design, and electronic design automation, M31 delivers world-class solutions inhigh-speed interface IPs, memory compilers, and standard cell libraries . For more information, please visit www.m31tech.com.Position: Staff Standard Cell Design EngineerLocation:Bengaluru, India Employment Type:Full-time | On-siteRole SummaryM31 Technologies India Private Limited is seeking an experiencedStandard Cell Design Engineerto join our dynamic team in Bengaluru. The role involves designing and developingadvanced standard cell librariesfor cutting-edgeFinFET technology nodessuch as4nm, 3nm, and 2nm . The ideal candidate will bring strong technical depth incircuit design ,PPA optimisation , andcell architecture development , working collaboratively with global teams to deliver best-in-class IP solutions for next-generation SoCs.Key ResponsibilitiesDesign and developcomplex combinational and sequential standard cellsoptimised forpower, performance, and area (PPA) . Collaborate withEDA vendorsto enable and validate new synthesizable cell architectures. Enhancelibrary architecturesand optimise designs forlower FinFET nodes (3nm, 2nm) . Analysereliability, high-sigma, and timing sign-offparameters to ensure high-yield tape-outs. Work closely withimplementation teams (STA, P&R)to debug and improve critical path performance. Contribute totest chip design, silicon validation, and data correlationactivities. Applylow-power and high-speed design techniquesto achieve performance targets. Develop and maintain automation flows usingPerl, Python, or TCL scripting . Providetechnical guidance and mentorshipto junior design engineers.Required Qualifications5+ yearsof experience instandard cell circuit designacross FinFET technologies. Proven expertise incombinational and sequential cell development . Strong understanding ofPPA optimisation, design sign-off, and library characterisation . Hands-on experience withEDA toolsfor layout, timing, and simulation (Cadence, Synopsys, or equivalent). Sound knowledge ofSTA, place-and-route , andtiming closuremethodologies. Excellent problem-solving, analytical, and collaboration skills. Bachelor’s or Master’s degree inElectrical or Computer Engineering , preferably with a focus onVLSI design .Preferred QualificationsExperience working onFinFET nodes (4nm and below) . Knowledge ofreliability and high-sigma design techniques . Familiarity withCPU or GPU standard cell design . Proficiency inautomation and scripting(Perl, Python, TCL). Advanced degree (MTech/PhD) inElectrical or Computer Engineering .

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