RTL Design Engineer-CXL

RTL Design Engineer(CXL) Experience - 5+yrs Location- BangaloreJD Strong RTL designer with IP design experience SoC Integration Interconnect Generation for a given configuration CXL 3.1 and above design experience

Hi All,Job Location: Bangalore Notice Period: 15 days to 30 Days Minimum: 5+ Years 1.Experience in Low power RTL design, microarchitecture, synthesis, timing closure, Low power estimation. Should be proficient in Verilog. 2. Should have experience in optimization of microarchitecture and RTL for area and power reduction. Experience with Arithmetic units,...

Hi All,Job Location: Bangalore Notice Period: 15 days to 30 Days Minimum: 5+ Years 1.Experience in Low power RTL design, microarchitecture, synthesis, timing closure, Low power estimation. Should be proficient in Verilog. 2. Should have experience in optimization of microarchitecture and RTL for area and power reduction. Experience with Arithmetic units,...

LLTS is looking to hire for RTL design engineers with 6+ years of experience with below skills set ::RTL Design Engineer with 6+ of Hands on experiences.• Experience/proficiency in RTL design(Verilog/VHDL) architecture implementation using (coding in) hardware description (RTL) , IP Design, SoC Design and Integration• Should have hands on experience in...

Job Title: RTL Design Engineers Exp Level: 4+ yrs Loctaion: Hyderabad /BangaloreJob Description: • RTL coding knowledge • Top-level (SOC) level basic industry standard Arch knowledge • SoC & IP level Integration knowledge • IPXACT knowledge • IORING and Phys & GPIOs basic functionality • Design Partitioning(Tilification) knowledge • Design RTL...

Job Title - RTL Design Engineers Exp Level: 4+ yrs Loctaion: Hyderabad /Bangalore Job Description: • RTL coding knowledge • Top-level (SOC) level basic industry standard Arch knowledge • SoC & IP level Integration knowledge • IPXACT knowledge • IORING and Phys & GPIOs basic functionality • Design Partitioning(Tilification) knowledge • Design...

Job Description Responsibilities - Develop synthesizable RTL for high-performance SoC, subsystem, or IP designs APB - Contribute to architecture definition, micro-architecture design, and implementation - Collaborate closely with architecture, verification, and physical design teams ARM - Own and deliver RTL blocks from spec to tape-out - Ensure clean...

Job Title: RTL Design EngineersExp Level: 4+ yrsLoctaion: Hyderabad /BangaloreJob Description:• RTL coding knowledge• Top-level (SOC) level basic industry standard Arch knowledge• SoC & IP level Integration knowledge• IPXACT knowledge• IORING and Phys & GPIOs basic functionality• Design Partitioning(Tilification) knowledge• Design RTL quality...

Job Description ASIC RTL Design Engineer Job Description: Exp: 5 to 8 yrs Location: Hyderabad - Good knowledge on the digital concepts and ASIC flow - Experience in RTL coding is a must. - Must have hands on experience with SoC design and integration. - Experience in Verilog/System-Verilog is a must. - knowledge of AMBA protocols - AXI, AHB, APB - Basic...

Job Description:RTL Design ( Ethernet ) Experience : 5-8 years Location : HyderabadCandidate should be with strong RTL design experience. Strong design Experience in Ethernet IPs or Ethernet protocol domain. knowledge in Verilog/VHDL languages scripting languages TCL/Perl/python any one. Knowledge of AXI Protocols.