Principal Engineer

3 weeks ago

Bangalore Division, India Mulya Technologies Full time

Principal Engineer – Analog Design Location: Bangalore We are a US based MNC with Market Cap of 10+Billion USD With over many of semiconductor experience, we are a leading provider of high-performance products and innovations that maximize bandwidth, capacity and security for AI and other data-intensive workloads. Our world-class team is the foundation of our company, and our innovative spirit drives us to develop the cutting-edge products and technologies essential for tomorrow’s systems . We are a global company that makes industry-leading memory interface chips and Silicon IP to advance data center connectivity and solve the bottleneck between memory and processing We are a premier chip and silicon IP provider, is seeking to hire an exceptional Principal Engineer – Analog Design to join our memory interface chip design team in Bangalore. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer. As a Principal Engineer – Analog Design, the candidate will be reporting to Director Engineering and is a Full-Time position. The candidate will be leading the analog mixed signal circuit design activities for high-performance mixed signal chip products. our memory interface chips team delivers the most advanced chipset solutions for server memory sub-system. This role gives opportunities to invent solutions to improve performance of next generation high-performance mixed signal products and learnings opportunities working through all the phases of chip product design all the way from concept to volume production. Responsibilities: As a “Principal Engineer – Analog Design” in memory interface chip design team, you will Ownership of Analog/Mixed designs at chip and/or block level. Define optimal architectures to achieve competitive product specifications. Design, simulate and characterize high-performance and high-speed circuits (e.g. Transmitter, Receiver, LDO, PLL, DLL, PI circuits). Create high level models for design tradeoff analysis and behavior model for verification simulations. Create floorplan and work with layout team to demonstrate post extraction performance. Document analysis and simulation to show that design achieves critical electrical, timing parameters and pre-silicon verification flow. Mentor/Manage junior team members and cultivate a growth mindset among team to encourage collaboration & inclusion. Participate and drive post silicon validation, debug, and customer collaboration. Requirements/Qualifications: Master’s with 8+ years (or PhD with 6+ years) of experience in CMOS analog/mixed-signal circuit design. Prior experience in some of the following circuits: Transmitter, Receiver (with CTLE, DFE), PLL, DLL, PI, LDO regulators. Good knowledge of design principles for practical design tradeoffs. Knowledge of high-speed chip to chip interfaces (memory PHY, SerDes) is a strong plus. Experience in modeling (Verilog-A, Verilog) and scripting is desirable. The position requires good written & verbal communication skills as well a strong commitment and ability to work in cross functional and globally dispersed teams. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

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