Design Verification Engineer
2 weeks ago
Qualification Required :
- Typically requires minimum of 4-15 years of experience in System Verilog, UVM.
- Bachelors OR Master's Degree Engineering in Electronics or Electrical or Telecom or VLSI Engineering.
Roles And Responsibilities :
As a member of the design verification team, it is your job to break things. You will work with logic designers to test RTL modules using UVM and will have the opportunity to develop re-usable verification components and testbenches.
You will develop testbench components and stimulus using System Verilog UVM libraries. On a small, agile team, you will start from microarchitectural specifications and develop test environments and test plans to achieve code coverage targets. You will collaborate via design reviews and code reviews.
Required Technical And Professional Expertise :
- Hands on project experience with verification methodologies UVM
- Domain experience of PCI-e, AMBA, I3C and DDR protocols
- Hands on project experience in verifying SoC with C-SV/UVM based environments.
- Can understand clocking, reset architecture and data flows. Has knowledge of SoC bring-up, bus protocol, register and address map Verification.
- Experience in coverage/assertion driven verification.
- Good knowledge of UNIX shell scripting, Perl and Python scripting
- Experience in writing verification plans and test bench development, simulation, and debugging.
- Proficient with CAE/CAD tools such as schematic capture, simulation, design verification
- Good analytical and problem-solving skill
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