DFT Engineer

4 weeks ago

Hyderabad, India Spruce IT Pvt. Ltd. Full time

Role : DFT Engineer.

Location : Pan India.

Main Skills : DFT, RTL, Verification.

Experience : 4+ Years.

Payroll : Spruce IT Pvt Ltd.

Notice Period : Immediate to 30 Days.

Job Description :

- Implementation tools like Mentor Tessent Fastscan, Testkompress or Synopsys DFT compiler and Tetramax.

- Sound knowledge of ATPG/Scan, coverage analysis, EDT compression etc.

- Sound debug skills to debug simulation failures at RTL-level and gate-level.

- Exposure to Static timing in DFT modes to debug constraint issues and review/analyze timing reports.

Key Responsibilities :


DFT Implementation :


- Utilize tools like Mentor Tessent Fastscan, Testkompress, Synopsys DFT Compiler, and Tetramax for DFT implementation.


- Develop and implement test strategies to ensure high-quality designs ATPG/Scan and


Coverage Analysis :


- Perform Automatic Test Pattern Generation (ATPG) and scan insertion.


- Conduct coverage analysis to ensure adequate test coverage and identify areas for improvement.


- Implement and manage EDT (Embedded Deterministic Test) compression techniques to optimize test data volume and test time.


Memory BIST Implementation and Verification :


- Implement and verify Memory Built-In Self-Test (BIST) solutions.


- Ensure robust and reliable testing of memory components within the design.


Debugging and Simulation :


- Debug simulation failures at RTL-level and gate-level.


- Analyze and resolve issues arising during DFT implementation and testing.


Static Timing Analysis :


- Perform static timing analysis in DFT modes to identify and debug constraint issues.


- Review and analyze timing reports to ensure the design meets all timing requirements.


Qualifications :


- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.


- Proven experience with DFT implementation tools such as Mentor Tessent Fastscan, Testkompress, Synopsys DFT Compiler, and Tetramax.


- Strong understanding of ATPG/Scan, coverage analysis, and EDT compression techniques.


- Experience with Memory BIST implementation and verification.


- Excellent debugging skills, with the ability to troubleshoot and resolve simulation failures at both RTL-level and gate-level.


- Familiarity with static timing analysis in DFT modes and the ability to debug and analyze timing reports.


- Strong problem-solving skills and attention to detail.


- Excellent communication and teamwork skills.


Preferred Qualifications :


- Experience in the semiconductor industry.


- Knowledge of industry-standard practices for DFT.


- Familiarity with additional DFT tools and methodologies.


Work Environment :


- Collaborative and innovative work environment.


- Opportunities for professional growth and development.


- Competitive compensation and benefits package.

(ref:hirist.tech)

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