RTL Integration Engineer
2 months ago
Job Responsibilities:
- Work with chip architect to understand architecture concept and high level requirements
- Convert chip spec to RTL using internal and external IPs
- Plan and deliver RTL for continuous integration testing
- Support the verification team to devise appropriate test plans and verification strategy
Job Requirements:
- Experience in ASIC/SoC front-end (preferably RTL Verilog and VHDL based) design and methodologies.
- Earlier experience with SoC Integration, Processor based architectures needed.
- Self-driven and capable of independent work and independent decision making.
- Knowledge in frontend design experience on IPs involve processor based sub-system, Serial Standard interfaces, Memory controllers
- Exposure to Low-power design, System Security considered as added advantage
- Hands on front-end design of complex multi clock domain blocks
- Fluency in design & verification languages such as VHDL, Verilog, C and System Verilog.
- Experience in Spyglass for lint and CDC checks.
- Experience in synthesis and LEC flow.
- Experience in identifying and implementing complex ECO in netlist.
- Defining and debugging timing constraints.
- Knowledge on Verification Methodologies to actively participate in Debug Analysis.
- Knowledge about system level flows and interaction with Firmware and Software would be an added advantage.
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