Design Verification Lead
2 weeks ago
Job Title : DV Lead Low Power (UPF)
Experience : 8+ years
Employment Type : Full-time
About the Role :
We are seeking a highly skilled Design Verification (DV) Lead with strong UPF (Unified Power Format) expertise to drive verification for low-power SoC/IP projects. The ideal candidate will have deep experience in power-aware verification methodologies, a strong background in System Verilog/UVM, and proven leadership in delivering IP/SoC verification signoff.
This is a senior technical leadership role with responsibility for guiding teams, driving methodology improvements, and ensuring first-pass silicon success.
Key Responsibilities :
- Lead low-power verification strategy for complex ASIC/SoC designs using UPF (IEEE 1801).
- Develop, validate, and maintain UPF-based power intent files for retention, isolation, power gating, and level shifters.
- Own IP-level and SoC-level verification signoff, ensuring power intent matches design implementation.
- Build and enhance System Verilog/UVM-based verification environments with power-aware simulation capabilities.
- Perform debug of power-aware simulation failures including X-propagation, wake-up sequences, power gating transitions, and retention logic.
- Collaborate with RTL, DFT, Synthesis, and Physical Design teams to ensure UPF constraints are correctly applied across design stages.
- Ensure comprehensive functional coverage and low-power coverage closure.
- Define and enforce verification best practices, coding guidelines, and methodology improvements.
- Mentor and guide junior DV engineers in low-power verification concepts and testbench development.
- Drive regression automation, scripting (Tcl/Python/Perl), and flow improvements for productivity.
- Provide technical leadership in reviews, planning, and signoff discussions with cross-functional teams.
Required Skills & Experience :
- 8+ years of experience in ASIC/SoC Design Verification.
- Strong hands-on expertise with UPF (Unified Power Format IEEE 1801).
- Proven experience in low-power verification methodologies (retention, isolation, level shifters, power gating).
- Strong knowledge of SystemVerilog and UVM methodology.
- Experience in IP-level verification and signoff.
- Hands-on with power-aware simulation tools (Synopsys VCS NLP, Cadence Xcelium LP, Mentor Questa LP).
- Excellent debugging skills in power-aware and functional simulations.
- Strong collaboration skills with RTL, STA, DFT, and P&R teams.
- Prior experience as a DV Lead or Senior DV Engineer with team mentoring.
Preferred Skills (Good to Have) :
- Experience in GLS (Gate-Level Simulation) for low-power designs.
- Exposure to formal verification techniques.
- Experience with Scripting (Tcl/Python/Perl) for regression automation.
- Familiarity with advanced technology nodes (7nm/5nm).
- Prior exposure to SoC verification (beyond IP level).
(ref:hirist.tech)-
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