Sykatiya Technologies

1 month ago


Hyderabad, India Sykatiya Technology Pvt Ltd Full time

Roles and Responsibilities :

- Work experience with node 7nm or lower node designs with advanced low power techniques is must.

- Experience on ASIC Physical Design : Floor planning, P&R, extraction, IR Drop Analysis, Timing and Signal Integrity closure, Physical Verification are essential part of the job.

- Well versed with Cadence or Synopsys tools is important.

- Experience with Static Timing Analysis in Primetime or Primetime-SI is important.

- Hands-on experience in scripting languages such as PERL, TCL is important.

- Timing closure on high-speed interfaces is a plus.

- Knowledge on Full chip Physical Design is beneficial.

- Good ASIC fundamentals and problem-solving skills is preferred.

Mandatory Skills :

- Experience with 7nm node.

- Experience with Cadence Innovus

(ref:hirist.tech)
  • Sykatiya Technology

    3 weeks ago


    Hyderabad, India Sykatiya Technology Pvt Ltd Full time

    About Company Profile :Sykatiya Technologies provides an extensive set of quality and timely VLSI Design, TEST Services & Specialized Solutions. These services range from a full turnkey solution that delivers a production-ready design, to sub-system or IP block development, or having our engineers augment your existing design teams with specialist design,...

  • Sykatiya Technology

    4 weeks ago


    Bangalore/Hyderabad/Chennai, IN Sykatiya Technology Pvt Ltd Full time

    About Company Profile :Sykatiya Technologies provides an extensive set of quality and timely VLSI Design, TEST Services & Specialized Solutions. These services range from a full turnkey solution that delivers a production-ready design, to sub-system or IP block development, or having our engineers augment your existing design teams with specialist design,...

  • Sykatiya Technology

    3 weeks ago


    Bangalore/Hyderabad/Chennai, India Sykatiya Technology Pvt Ltd Full time

    About Company Profile : Sykatiya Technologies provides an extensive set of quality and timely VLSI Design, TEST Services & Specialized Solutions. These services range from a full turnkey solution that delivers a production-ready design, to sub-system or IP block development, or having our engineers augment your existing design teams with specialist design,...

  • Sykatiya Technologies

    4 weeks ago


    Bangalore/Hyderabad, Karnataka, India Sykatiya Technology Pvt Ltd Full time

    Roles and Responsibilities : - Work experience with node 7nm or lower node designs with advanced low power techniques is must.- Experience on ASIC Physical Design : Floor planning, P&R, extraction, IR Drop Analysis, Timing and Signal Integrity closure, Physical Verification are essential part of the job.- Well versed with Cadence or Synopsys tools is...

  • Sykatiya Technologies

    1 month ago


    Bangalore,Hyderabad, India Sykatiya Technology Pvt Ltd Full time

    Roles and Responsibilities : - Work experience with node 7nm or lower node designs with advanced low power techniques is must.- Experience on ASIC Physical Design : Floor planning, P&R, extraction, IR Drop Analysis, Timing and Signal Integrity closure, Physical Verification are essential part of the job.- Well versed with Cadence or Synopsys tools is...

  • Sykatiya Technologies

    4 weeks ago


    Bangalore/Hyderabad, Karnataka, India Sykatiya Technology Pvt Ltd Full time

    Roles & Responsibilities :1. You will be exposed to the latest verification methodologies like UVM and enable complex feature verification suites. 2. Architect and Develop block level verification environments for sub-system and fullchip using System Verilog and UVM methodology. 3. Define, architect, code, and deliver verification suites/tests for ASICs that...

  • Sykatiya Technologies

    1 month ago


    Bangalore,Hyderabad, India Sykatiya Technology Pvt Ltd Full time

    Roles & Responsibilities : 1. You will be exposed to the latest verification methodologies like UVM and enable complex feature verification suites. 2. Architect and Develop block level verification environments for sub-system and fullchip using System Verilog and UVM methodology. 3. Define, architect, code, and deliver verification suites/tests for ASICs...