ASIC RTL Engineer

1 month ago

Bengaluru, India Tech Mahindra Full time

Hiring ASIC RTL Design Engineers


Experience : 4-20 years

Location: Kochi/Ahmedabad/Bangalore/Vizag

· Architecture Development

o Experience in developing High Level Architecture for a Design Requirement from Specification level

o Extract Micro Architecture from High Level Architecture specification

· RTL Design - Coding & Integration

o Develop the logic design and Implement register transfer level (RTL) coding for an IP / SoC design

o Optimize logic to qualify the design to meet power / performance / area / timing goals and ensure Design Integrity

o Build unit level tests to verify the initial design –

o Ensure designs are delivered on time and with the highest quality by using proper checks

o Provide Hand-off to Subsystem / SoC Owners for IP Integration

o Integrate logic of IP blocks and subsystems into a full chip SoC or discrete component design

o Work with different IP providers to integrate and validate IPs at the Subsystem or SoC level

o Review verification plan and implementation to ensure design features are verified correctly

o Work closely with Verification team on Feature Extraction, Test Plan Review & sign-off closures

o Resolve and implement corrective measures for failing RTL tests to ensure correctness of features

· RTL Quality Checks

o Perform quality checks on various logic design aspects ranging from RTL to timing/power convergence.

o Hands on experience in running Synopsys Fusion Compiler for Synthesis and Area and performance estimation

o Perform RTL Lint check, Equivalence checking, CDC checking and support Static Timing Analysis, Static Power Checks,

o Work closely with different Product owners (Design team / Tool Team / Vendors etc., ) to resolve Design (or) Flow issues

o Triage all violations for a given Quality check - Accurately Identify & Root Cause issues in design and provide solutions

o Own the RTL QC task for a given IP / Subsystem / SoC – Ensure periodic checks & Clean up issues with new RTL Drops iteratively

o EDA Tool Exposure :

§ VCS Compile, SG Lint, SG CDC, Synthesis DC / FC Compiler

§ VC LP, Conformal LEC, SAGE Coverage, Calibre, Fishtail

§ Integration Tools - Collage / DeFacto

·Scripting & Automation Exposure

o Knowledge / Working Experience on Perl, Tcl, Shell scripting is an added advantage

o Knowledge / Working Experience on debugging Tool Flows & Setup related issues is an added advantage

·Protocol Knowledge (IPs / Processors / IO Bus Protocols etc., )

o Ability to Understand complex SOC architecture concepts through work experience

o Protocol Knowledge – PCIe, CXL, USB, Ethernet, DDR, HBM MIPI, RISC etc.,


Please share your profile to jhansi.bv@techmahindra.com for further discussion.

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