Layout Designer
4 weeks ago
This is Jr position., If you are meeting with below criteria means pls share your resume to karthik.ravichandran@hays.com.au with below details.. Over all experience; Relevant experience; CCTC; ECTC; Current location; Will you able to attend final round in F2F at Bangalore; Location; Bangalore Role; Custom Standard Cell Design Engineer Final round must be F2F. Job Description You will be responsible for the development of Arm custom standard cells in the latest, sub-3nm process technology nodes. You will work as part of a team that co-optimizes the circuit design with physical design engineers to improve the PPA of Arm cores that will be integrated into best-in-class SoCs. You will work in close collaboration with the mask design team to provide optimally tuned layout, characterize and model all standard libra Required Skills and Experience : 2+ years of relevant circuit design experience (for BSEE)1+ years of relevant circuit design experience (for MSEE) Experience in the identification, design and verification of cells specifically targeted to improve core and SoC level PPA In-depth understanding of MOSFET electrical characteristics, transistor level device physics, PPA trade-offs, layout and variability especially at 3nm and below technology nodes Expertise in transistor level design of static circuits including state retaining elements such as latches and flops Hands-on development of standard cell EDA view characterization, modeling and QA Experience with standard cell characterization tools and Spice circuit simulators Familiarity with scripting languages such as Perl or Python Be willing to iteratively improve designs and repeatedly attempt to develop solutions to difficult problems Demonstrate a positive attitude and respect for all members of the team Be motivated to continuously develop skills and accept various responsibilities as a part of contributing to Arm’s success Ability to analyze data and present conclusions effectively An engineer with 1–4 years of experience in standard cell or custom circuit design , strong knowledge of CMOS device physics and transistor-level design , and hands-on expertise in SPICE simulation and cell characterization tools like Cadence Liberate or Synopsys SiliconSmart . Skilled in Python/Perl scripting , familiar with advanced process nodes (≤5nm) , and capable of PPA optimization through close collaboration with layout and physical design teams.
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PCB Layout Designer
2 weeks ago
Bangalore Division, India ACL Digital Full timePCB Layout Designer Experience : 6-10 years Location : Bangalore Key Skill Requirements: • Individual project handling: The designer must be capable of handling individual projects from conceptualization to completion. • Tool expertise: The PCB designer must demonstrate expertise in using the Cadence Allegro tool for PCB design and basic knowledge of...
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Senior Analog Layout Design Leads
4 days ago
Bangalore Division, India Eximietas Design Full time🌟 We’re Hiring! Senior Analog Layout Design Engineers / Leads 🌟 Location: Bangalore/Visakhapatnam Experience: 5-15 Years Notice Period: 30 days or less preferred Greetings from Eximietas Design ! We’re expanding our Analog Layout team and looking for talented engineers who are passionate about delivering world-class designs in advanced FINFET...
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Senior Analog Layout Design Leads
2 weeks ago
Bangalore Division, India Eximietas Design Full timeHi Greetings from Eximietas Design! We are actively looking to hire Senior Analog Layout Design Engineers / Leads with 8-14 years of experience to join our growing team. 📍 Locations: Bangalore. 📅 Notice Period: 30 days or less preferred. Job Description: We’re seeking highly skilled professionals with a strong background in lower FINFET technology...
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Analog Layout Engineer
4 weeks ago
Bangalore Division, India ACL Digital Full timeAnalog Layout Engineer Required Qualifications: Bachelor’s or Master’s degree in Electrical Engineering , Computer Engineering , or a related field. 4+ years of experience in analog layout design with a focus on TSMC 7nm , 5nm , and 3nm process technologies. Proficiency with Cadence Virtuoso , Mentor Graphics , Synopsys IC Compiler , or equivalent analog...
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Memory Layout Engineer
2 weeks ago
Bangalore Division, India Capgemini Engineering Full timeRole: Memory/Custom Layout Engineer Experience: 3 to 12 Years Location: Bengaluru Job Description: 3-8 years of experience in Memory/Custom Layout design. Memory Leafcell layout library design from scratch including top level integration. Good knowledge on different types of memory architectures. Good knowledge in optimized layout design for better...
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AMS Layout
3 weeks ago
Bangalore Division, India ACL Digital Full timeACL Digital is looking for an Experienced Layout Engineer Minumum 4+ years of Experience for Bangalore Location Good to have ESD Blocks Must have Lower nodes from TSMC AMS/IO Memory - Layout Interested share/refer karthick.v@acldigital.com Bachelor's or Master's Degree with 4 - 12 years of Analog Layout experience Demonstrated leadership experience of at...
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Analog Layout Engineer
3 weeks ago
Bangalore Division, India ACL Digital Full timeHi All, Title : Analog Layout Engineer Exp Level:3+ yrs Location: Bangalore Job Description: Design and development of full custom analog/mixed-signal layout at block and top level. Strong expertise in analog layout techniques for circuits such as ADC, DAC, PLL, LDO, Bandgap, etc. Hands-on experience with layout tools like Cadence Virtuoso, Calibre, and...
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Memory Layout Engineer
2 days ago
Bangalore Division, India ACL Digital Full timeMemory Layout Engineer Location: Bengaluru Experience Required: 3+ Years Employment Type: Full-Time Job Summary: We are seeking an experienced and detail-oriented Memory Layout Engineer with 3+ years of hands-on experience in custom layout design and verification of memory IPs (SRAM, ROM, CAM, etc.). The ideal candidate will have a strong background in...
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Senior Layout Design Engineer
4 days ago
Bangalore Division, India Proxelera Full time🔥 We’re Hiring: Full-Custom Memory Layout Expert (SRAM Compilers) 🔥 Are you passionate about turning complex circuits into clean, sign-off quality layouts ? This is your chance to lead full-custom memory layout for cutting-edge SRAM compilers! What you’ll do: ✅ Own layout creation for SRAM compiler blocks ✅ Drive physical verification (EM, IR,...
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Layout Design Engineer
2 weeks ago
bangalore, India KARMIC DESIGN PVT LTD Full timeJob SummaryWe are seeking a Senior Custom Layout Design Engineer with 5+ years of hands-on experience in analog/mixed-signal custom layout design. The ideal candidate should have strong expertise in high speed layout concepts and FinFET process nodes. You will be responsible for delivering high-quality layout designs and leading module-level layout...
