Senior Design Verification Engineer

Job Title: Design Verification Engineer

Location: Bangalore, India

Type - Full time

Description:

Client is seeking a Design Verification Engineer. The role is technical, hands-on, in charge of the verification environment for new silicon projects and developments. We are looking for an experienced professional with Passion & Drive to succeed.

Primary Responsibilities Include:

• Responsible for all aspects of verification methodology employed and for ensuring the application of uniform standards and adoption of best practices.
• Work and liaison with other Design Verification teams within our customer sites to identify holes in the design verification flow and implement corrective action.
• Overall, responsible for verification of ASIC designs To include such things as:
• Design Verification – Implement test benches in UVM and Sytem
• Verilog, run regressions at RTL and gate level, generate and report DV metrics with respect to bug tracking and code coverage, debug failures and provide feedback to the design team.
• Responsible for oversight and completion of debugging problems and troubleshooting in Real Time. This includes being responsible for
• Debugging Designs for High throughput, Low Latency of Pipeline and
• Dynamic Power Management at full system level.
• Setup Verification Regression suites at RTL Level & Corresponding
• Netlist Level after Synthesis to test any/all Corner case conditions.
• This may include: review of specifications, understanding chip architecture, developing tests & coverage plans, and defining methodology & test benches.

Necessary Qualifications:

• BS or MS in Computer Science or Electrical Engineering.
• 5-10+ years of industry experience bringing silicon ICs into high volume production.
• Must have strong experience with UVM.
• Must have a full chip verification experience
• Experience of leading a single project.
• Knowledge of industry standard interfaces. Extensive Familiarity with
• Verilog, Simulation tools & demonstrated ability to debug Problems &
• Troubleshooting in Real Time.
• Sound knowledge of ARMv8, interconnect, memory coherence and memory architectures
• Familiarity with Formality & most popular Verification Tools. (Key knowledge should include such topics as: IP validation, Gate level verification, FPGA Validation, Emulation, Silicon Validation, Reference Board bring up verification, Silicon Bring up, DFx, Low Power Verification)
• Expertise in writing Perl / Python, awk, sed & Common Scripts to automate the Verification Tasks for CPU plus all Chip peripherals – USB, PCIe, MIPI,
• SDIO, PCI E & DDR Controllers.
• Advanced knowledge of ASIC design and verification flow including RTL design, simulation, test bench development, regression, equivalence checking, timing analysis, scan insertion and test pattern generation
• Experience with low-level programming of systems in C/C++.
• Experienced in writing scripts in languages such as Perl, Python, and Tcl.
• Functional understanding of constrained random verification process, functional coverage, and code coverage.
• Low power verification UPF
• Team player with excellent communication skills and the desire to take on diverse challenges.
• Customer interaction

Other Qualifications:

• Good knowledge of low power cameras and imaging systems is a plus
• Experience with formal verification tools is a plus.
• CPU Security, Secure boot, Secure JTAG
• Familiarity with ARM architecture
• Familiarity with scripting/programming with Perl/Python, Tcl, C/C++