IP Verification Technical Lead

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ ABOUT THE DEPARTMENT Central DFX (CDFX) is a centralized ASIC design group within AMD’s Technology and Engineering organization. CDFX has a global footprint with design teams located in several AMD offices in North America and Asia. Our mandate is to optimize and standardize design methodology, design and implementation of critical Design-for-Test (DFT) and Design-for-Debug (DFD) features for high performance, adaptive compute products for data center, embedded, gaming and PC markets. It is also responsible for DFX design methodology and CAD automation tools development to support the global DFX engineering teams across AMD. PMTS SILICON DESIGN ENGINEER THE ROLE We are seeking an experienced design verification engineer with strong technical and leadership skills, who thrives in a fast-paced environment, to lead a talented team of engineers responsible for developing an efficient, scalable UVM based verification environment to exercise large, complex IP blocks. THE PERSON: In this role, you will lead a high-performance central design team through the full verification lifecycle of a state of-the-art industry leading Debug IP, from planning and implementing innovative verification strategies to collecting and closing coverage. You will establish a collaborative environment that fosters innovation and verification best practices. In addition to managing project schedules, deliverables, dependencies, and risk mitigation plans, you will mentor, provide technical guidance, and further develop the team. The ideal candidate has experience leading others in technical and managerial settings. You also have excellent communication, writing, and presentation skills. A global mindset and ability to lead in a multi – site environment are keys to being successful in this role. KEY RESPONSIBILITIES: Lead the CDFX DV team at AMD Bangalore Office to perform the Debug IP verification, which includes: IP level test plan creation and development, conducting and participating in test plan reviews developing scalable verification components, random-constrained stimulus, and debugging regression failures Code reviews and DV coverage analysis Provide technical guidance and innovative ideas to improve quality, processes, and productivity Manage DV execution: project planning, IP delivery timelines, deliverables and quality checks track project progress and ensure projects stay on track for timely completion resource planning, critical path analysis, risks identification and mitigation plan Technical support to SOC teams (internal customers) on Debug IP deliverables and tape out readiness signoff Collaborate with cross-functional leaders to drive AMD's success Strategic team development plan creation Team performance review and management Guide and develop people at several different levels of experience to encourage career growth Talent recruiting. Occasional short-term international travel upon per business need PREFERRED EXPERIENCE: 11-15 years of Experience leading verification teams on complex CPU/ASIC projects from inception to tape-out Solid understanding of functional design verification, including but not limited to test bench architecture, tool integration, coverage, power domains, random constrained testing, and debug. Excellent organizational and project management skills Proven experience managing and leading engineering teams Strong communications skills. Able to summarize complex problems for executives as well as drill down to details with architects and engineers Strong analytic and problem-solving skills including the ability to analyze current behavior, identify potential areas for improvement and design of experiments Must be a self-starter and self-motivated ACADEMIC CREDENTIALS: BTECH/BE/BS, MTECH/ME/MS, or PhD degree in Electrical or Computer engineering. Advance degree preferred. LOCATION: Bangalore, India #LI-RR1 #LI-Hybrid Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.ABOUT THE DEPARTMENT Central DFX (CDFX) is a centralized ASIC design group within AMD’s Technology and Engineering organization. CDFX has a global footprint with design teams located in several AMD offices in North America and Asia. Our mandate is to optimize and standardize design methodology, design and implementation of critical Design-for-Test (DFT) and Design-for-Debug (DFD) features for high performance, adaptive compute products for data center, embedded, gaming and PC markets. It is also responsible for DFX design methodology and CAD automation tools development to support the global DFX engineering teams across AMD. PMTS SILICON DESIGN ENGINEER THE ROLE We are seeking an experienced design verification engineer with strong technical and leadership skills, who thrives in a fast-paced environment, to lead a talented team of engineers responsible for developing an efficient, scalable UVM based verification environment to exercise large, complex IP blocks. THE PERSON: In this role, you will lead a high-performance central design team through the full verification lifecycle of a state of-the-art industry leading Debug IP, from planning and implementing innovative verification strategies to collecting and closing coverage. You will establish a collaborative environment that fosters innovation and verification best practices. In addition to managing project schedules, deliverables, dependencies, and risk mitigation plans, you will mentor, provide technical guidance, and further develop the team. The ideal candidate has experience leading others in technical and managerial settings. You also have excellent communication, writing, and presentation skills. A global mindset and ability to lead in a multi – site environment are keys to being successful in this role. KEY RESPONSIBILITIES: Lead the CDFX DV team at AMD Bangalore Office to perform the Debug IP verification, which includes: IP level test plan creation and development, conducting and participating in test plan reviews developing scalable verification components, random-constrained stimulus, and debugging regression failures Code reviews and DV coverage analysis Provide technical guidance and innovative ideas to improve quality, processes, and productivity Manage DV execution: project planning, IP delivery timelines, deliverables and quality checks track project progress and ensure projects stay on track for timely completion resource planning, critical path analysis, risks identification and mitigation plan Technical support to SOC teams (internal customers) on Debug IP deliverables and tape out readiness signoff Collaborate with cross-functional leaders to drive AMD's success Strategic team development plan creation Team performance review and management Guide and develop people at several different levels of experience to encourage career growth Talent recruiting. Occasional short-term international travel upon per business need PREFERRED EXPERIENCE: 11-15 years of Experience leading verification teams on complex CPU/ASIC projects from inception to tape-out Solid understanding of functional design verification, including but not limited to test bench architecture, tool integration, coverage, power domains, random constrained testing, and debug. Excellent organizational and project management skills Proven experience managing and leading engineering teams Strong communications skills. Able to summarize complex problems for executives as well as drill down to details with architects and engineers Strong analytic and problem-solving skills including the ability to analyze current behavior, identify potential areas for improvement and design of experiments Must be a self-starter and self-motivated ACADEMIC CREDENTIALS: BTECH/BE/BS, MTECH/ME/MS, or PhD degree in Electrical or Computer engineering. Advance degree preferred. LOCATION: Bangalore, India #LI-RR1 #LI-Hybrid
Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

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