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Senior DFT Engineer

3 months ago

Bengaluru, India VIDPRO CONSULTANCY SERVICES Full time

About the job :

Location : Bangalore, Mumbai

Experience : 5+ years

Job Description :

We are seeking a talented Senior DFT Engineer or Lead to join our dynamic team in Bangalore and Mumbai. As a key member of our Design for Test (DFT) team, you will be responsible for implementing DFT architectures, leveraging your expertise in JTAG, Scan Compression Techniques, and Synopsys tools.

This role requires a deep understanding of DFT methodologies and a proven track record in delivering high-quality designs.

Key Responsibilities :

- Develop and implement DFT architectures for complex ASIC and SoC designs.

- Design and implement JTAG interfaces and protocols.

- Utilize Scan Compression Techniques (i.e., ATPG, MBIST) to optimize test pattern generation and reduce test time.

- Collaborate closely with design and verification teams to ensure DFT requirements are met.

- Perform DFT insertion, including Scan Insertion, ATPG, and Memory BIST insertion.

- Validate and debug DFT features and functionalities.

- Utilize Synopsys tools (ie., DFT Compiler, TetraMAX) for DFT implementation and verification.

- Develop and maintain DFT documentation, including DFT specifications and test plans.

- Stay updated with the latest advancements in DFT methodologies and technologies.

Required Skills And Qualifications :

- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.

- 5+ years of experience in DFT engineering roles.

- Strong understanding of DFT architectures, including JTAG and Scan Compression Techniques.

- Proficiency with Synopsys DFT tools such as DFT Compiler, TetraMAX, and SpyGlass DFT.

- Experience in ATPG, MBIST, and other DFT techniques.

- Solid understanding of ASIC and SoC design flow and methodologies.

- Excellent problem-solving and analytical skills.

- Strong communication and interpersonal skills, with the ability to work in a collaborative team environment.

Preferred Skills :

- Experience with Mentor Graphics DFT tools (i,e., Tessent).

- Familiarity with RTL design and verification.

- Knowledge of FPGA prototyping and emulation.

- Experience in leading or mentoring junior engineers.

Benefits :

- Competitive compensation package including salary, bonus, and benefits.

- Opportunity to work on cutting-edge ASIC and SoC designs with industry leaders.

- Career growth and advancement opportunities in a fast-growing organization.

(ref:hirist.tech)