Lead System Validation
1 month ago
What we do :
• Pre Silicon emulation and Verification of System in NCSIM/Palladium/other Simulators.
• Hardware and Subsystem Board Design for all the Projects. (HW/SW infrastructure designed within team)
• Prototyping and Firmware Development for our High Speed Serdes like PCIe, CXL , UCIe, USB ,ethernet.
• Lead the Bring up, Debug, Compliance efforts and System level Characterization all the way to report release.
• Engage in interop and Customer Debug.
What you'll gain :
• Chance to work on cutting edge SERDES IP's from Cadence. Refer to Cadence Website for more details on our SERDES IP's.
• Tremendous learning curve on SERDES PHY, Controllers, Protocol and System integration.
• Hardware and Subsystem design expertise.
• Experience in deploying and debugging your Solutions in different customer environments.
What we are looking for :
Minimum Qualifications:
• 5-7 years (with Btech) or 5 years (with Mtech) experience in Post-Silicon PHY, Systems Interop and Compliance testing.
• Physical Layer and Protocol layer experience on AT LEAST ONE High speed SERDES on PCIe/CXL/UCIe/Ethernet.
• Debug skills and Experience in using lab equipment such as Oscilloscopes, Bit Error Rate Testers, Protocol Exercisers, Analyzers.
Preferred Qualifications:
• Experience in PCIe/UCIe LTSSM states is a plus.
• 1-2 years of experience in FPGA Design and Schematic design is a plus.
• 1-2 years of IP/SoC Physical Layer Electrical Validation experience is a plus.
• Familiarity with Verilog RTL coding for FPGA, python,C/C++
• Good communication skills
• Candidates are expected to be passionate about analog and digital electronic circuit design.
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