Physical Verification Engineer

4 days ago


New Delhi, India ACL Digital Full time

Physical Verification EngineerExperience: 2 to 5 Years Location: Bangalore Notice Period: ImmediateJob DescriptionKey Responsibilities: PerformPhysical Verificationchecks includingDRC, LVS, ERC , andAntennachecks atblock and full-chip level . Work withfoundry rule decks(TSMC / Samsung / GF / Intel / UMC etc.) to ensure design sign-off compliance. Debug and resolvelayout violationsby working closely with the Physical Design, Layout, and Circuit teams. RunParasitic Extraction(PEX) and support timing and SI closure teams for accurate model generation. PerformDFMchecks and assist with design enhancements for manufacturability. Supporttape-out preparation , validation, reports, checklists, and documentation. Required Skills & Expertise: Strong working experience withCalibre / PVS / ICVfor DRC & LVS sign-off. Understanding of CMOS layout fundamentals, standard cells, macros, and routing architectures. Familiarity withGDS / OASISdata formats, hierarchical layout structures, and physical design flows. Basic knowledge ofSTA, IR/EM, PDN, and PnR flowsis a plus. Ability to collaborate in cross-functional teams and drive closure of PV issues. Good to Have: Experience withadvanced technology nodes(7nm / 5nm / 3nm). Scripting inTcl, Python, or Shellto automate verification workflows. Exposure toCustom LayoutorAnalog/Mixed-signal PVenvironments. Education: B.E / B.Tech / M.E / M.Tech inElectronics / VLSI / Electrical / Semiconductoror related domain.



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