DFT Lead/Manager

Required Skills and Experience: DFT Engineering Manager with demonstrated hands-on experience in any areas of DFT – BIST, ATPG, Post-Silicon Debug, Boundary Scan etc. for at least 10 years Manage a team of high calibre DFT engineers and have excellent customer management skills. Working closely with the management to Hire talented, passionate, and...

DFT Technical LeadJob DescriptionExperience: 10+ years- Should have worked hands-on extensively on full chip DFT design,implementation, vector generation/verification, JTAG, boundary scan and simulation.-Experience with Scan, Compression, ATPG and simulations with Mentor/Synopsys/Cadence tools. Logic BIST knowledge is a plus.- Should have participated in...

DFT Technical LeadJob DescriptionExperience: 10+ years- Should have worked hands-on extensively on full chip DFT design,implementation, vector generation/verification, JTAG, boundary scan and simulation.-Experience with Scan, Compression, ATPG and simulations with Mentor/Synopsys/Cadence tools. Logic BIST knowledge is a plus.- Should have participated in...

DFT Technical LeadJob DescriptionExperience: 10+ years- Should have worked hands-on extensively on full chip DFT design,implementation, vector generation/verification, JTAG, boundary scan and simulation.-Experience with Scan, Compression, ATPG and simulations with Mentor/Synopsys/Cadence tools. Logic BIST knowledge is a plus.- Should have participated in...

DFT Technical LeadJob DescriptionExperience: 10+ years- Should have worked hands-on extensively on full chip DFT design,implementation, vector generation/verification, JTAG, boundary scan and simulation.-Experience with Scan, Compression, ATPG and simulations with Mentor/Synopsys/Cadence tools. Logic BIST knowledge is a plus.- Should have participated in...

DFT Technical Lead Job Description Experience: 10+ years - Should have worked hands-on extensively on full chip DFT design, implementation, vector generation/verification, JTAG, boundary scan and simulation. -Experience with Scan, Compression, ATPG and simulations with Mentor/Synopsys/Cadence tools. Logic BIST knowledge is a plus. - Should have...

Hands on experience with DFT of multimillion gate SoC designs in cutting edge process technologies (40nm, 28nm, 14nm) Should have experience in DFT and ATPG activities on SoC designs with expertise in MBIST Planning/Insertion, Partitioning Design for Scan, Scan Insertion, Compression, Wrapper Insertion, ATPG Simulations Expertise in handling...

DFT Technical LeadJob DescriptionExperience: 10+ years- Should have worked hands-on extensively on full chip DFT design,implementation, vector generation/verification, JTAG, boundary scan and simulation.-Experience with Scan, Compression, ATPG and simulations with Mentor/Synopsys/Cadence tools. Logic BIST knowledge is a plus.- Should have participated in...

Job Overview :We are seeking a highly experienced Senior DFT Engineer/Lead to join our team at Sykatiya Technology Pvt Ltd. As a key member of our design team, you will be responsible for leading the development of advanced digital fault tolerance (DFT) strategies and test programs for complex system-on-chip (SoC) designs.About the Role :The successful...

DFT Technical LeadJob DescriptionExperience: 10+ years- Should have worked hands-on extensively on full chip DFT design,implementation, vector generation/verification, JTAG, boundary scan and simulation.-Experience with Scan, Compression, ATPG and simulations with Mentor/Synopsys/Cadence tools. Logic BIST knowledge is a plus.- Should have participated in...

DFT Technical Lead Job Description Experience: 10+ years - Should have worked hands-on extensively on full chip DFT design, implementation, vector generation/verification, JTAG, boundary scan and simulation. -Experience with Scan, Compression, ATPG and simulations with Mentor/Synopsys/Cadence tools. Logic BIST knowledge is a plus. - Should have...

About the JobWe are seeking a highly skilled Senior DFT Lead to lead our team in designing and implementing complex SoC designs.Key Responsibilities:Lead DFT activities for multimillion gate SoC designs in cutting-edge process technologies (40nm, 28nm, 14nm)Develop and implement DFT strategies, including MBIST planning/insertion, partitioning design for...

About Company Profile :Sykatiya Technologies provides an extensive set of quality and timely VLSI Design, TEST Services & Specialized Solutions. These services range from a full turnkey solution that delivers a production-ready design, to sub-system or IP block development, or having our engineers augment your existing design teams with specialist design,...

About LeadSoc Technologies Pvt LtdWe are a leading company in the field of electronic design automation, specializing in Design for Test (DFT) solutions. Our team is committed to delivering high-quality products and services that meet the needs of our customers.

**ASIC Verification - 4-7 yrs** Requirment: Experience working of SV and UVM methodology and experience of at least one industry standard protocols like Ethernet, PCIe, MIPI, USB or similar is required, must have executed at-least 2 SoC Verification projects. **ASIC Verification Lead - 8-15 yrs** Requirment: Experience working of SV and UVM methodology...

Company Overview: eInfochips, an Arrow company, is a leading global provider of product engineering and semiconductor design services with 25+ years of proven track record.Estimated Salary Range: ₹2,500,000 - ₹3,500,000 per annum (based on industry standards for a senior physical design engineer in India)Job Description:">Responsible for floor-planning,...

Role Proficiency: Execute any internal project or small tasks of customer project in any field of VLSI Frontend Backend or Analog design under mínimal supervison from the Lead Outcomes: - As an Individual contributor work on any one task of RTL Design/Module in Verification/PD/DFT/Circuit Design/Analog Layout/STA/Synthesis/Design Checks/Signoff etc. -...

About the RoleWe are seeking an experienced Senior Physical Design Engineer to join our team at eInfochips (An Arrow Company). As a key member of our design team, you will be responsible for delivering high-quality ASIC designs from RTL-to-GDSII.Job DescriptionIn this role, you will be responsible for:Floor-planning, timing constraints, physical synthesis,...

Hands on experience with Implementation (PnR & Signoff) of multimillion gate SoC designs in cutting edge process technologies (40nm, 28nm, 16nm, 10nm) Lead all aspects of SoC Physical Design with strong expertise in the area of chip/partition floor-planning, design partition creation, budgeting and feedthrough planning Work alongside RTL/Synthesis/DFT...

Company OverviewWe are INVECAS, a leading technology company committed to innovation and excellence in the field of microarchitecture design.SalaryThe estimated annual salary for this position is $120,000 - $180,000, depending on experience and qualifications.Job DescriptionThis is an exciting opportunity to lead our team of IP/SOC design engineers in the...