Senior Analog Layout

Job Description5+ experience in Analog layouts in advanced nodes (16nm/10nm/7nm/5nm/3nm).• Should have experience on block level, IP level and chip level layouts.• Should have hands-on experience in creating layout of critical blocks such as LDO,ADC,DAC,Bandgap,Buck and boost converters etc..• Good understanding of analog layout fundamentals such as

About the RoleWe are looking for an experienced Analog Layout Engineer with strong hands-on exposure to TSMC advanced technology nodes. The candidate should have a solid understanding of full-chip and block-level layout for high-performance analog/mixed-signal IPs. Key ResponsibilitiesPerform layout design for Analog, Mixed-Signal, and Custom circuits such...

Analog LayoutLocation: Bangalore / HyderabadJob Description:TSMC 16/12nm,7nm,5nm,3nm and below (other foundries are also fine like Intel, Samsung, GF). Preferably TSMC 5nm/3nm experience.Responsible for Design and development of critical analog, mixed-signal, custom digital block and full chip level integration support.Verification flows –...

We're hiring Analog Layout Engineers (3–7 years) with hands-on experience in lower technology nodes, layout design, and DRC/LVS verification. Location: Hyderabad. Immediate joiners preferred.

Must have 3-5 of experience instandard cell layout, analog, mixed-signal and custom digital blockdesigns in advanced CMOS process. Should have expertise inmultiple standard cell layout library developments. Should be ableto perform standard

The Allegro team is united by a clear purpose—advancing technologies that make the world safer, more efficient, and more sustainable. With over 30 years of experience in semiconductor innovation, we bring that purpose to life across every part of the business—from breakthrough product development and customer success to how we show up for each other and...

i)Analog Layout EngineerSkills: who worked on Lower nodes 3nm, 5 nm, 7 nm, 10 nmExp: 4-9yrsLoc: HYDii) Skills: Non intel ExpExp:6+yrsLoc: BLRiii)Skills: finfet nodesExp:8+yrsLoc: BLR

Analog / Custom Layout Design Engineer (TSMC 3nm | FinFET | Cadence | Calibre)Experience: 4 to 8 YearsLocation: HyderabadJob Description:We are seeking a highly skilled Analog / Custom Layout Design Engineer to drive the design and development of critical analog, mixed-signal, and custom digital layouts, supporting full-chip level integration in advanced...

Responsibilities:Analog block or analog system design, from specification definition, high-level analysis, detailed transistor-level design, simulation, optimization, test to support to production. (40%)Design & optimization, verification, technical documentation, layout supervision. (20%)Silicon lab evaluation, characterization and debug. (10%)Block or...

The Allegro team is united by a clear purpose—advancing technologies that make the world safer, more efficient, and more sustainable. With over 30 years of experience in semiconductor innovation, we bring that purpose to life across every part of the business—from breakthrough product development and customer success to how we show up for each other and...