Physical Design Engineer
4 weeks ago
- ASIC Physical Design Engineer with 7+ years of Experience in Physical Design -Placement and Routing, Floor Planning, Static Timing Analysis & Physical Verification.
- Experience in lower design nodes and design technologies like 3nm, 8lpp,11lpp,16nm,65nm and 90nm.
- Excellent knowledge of ASIC design flow
- Familiar with scripting languages, VLSI designs, and Physical optimization
- Hands on experience on EDA tools like Cadence (Innovus/Stylus), Mentor (Calibre), PVS, Voltus
- Block level timing closure.
- Resolving various block level P&R issues
- Sound knowledge of static timing analysis and determination of timing fixes to achieve timing closure
- Excellent verbal and written communication skills, ability to deal with people diplomatically, willingness to learn Strong experience in block-level implementation.
- Strong experience in Floorplan, Placement, CTS, Routing, and Physical verification.
- Experience in Signoff- STA and Timing Closure.
- Hands-on with EDA tools like ICC2, Star-RC, Primetime
- Experience on lower node challenges.
- Experience on digital design and CMOS circuits
- Good team player & Highly adaptable
- Hardworking, good at organizing events and leadership qualities
(ref:hirist.tech)
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