Design Verification Engineer
5 hours ago
We’re hiring a SoC Verification Engineer with real hands-on muscle.
If you’ve spent 5+ years building and breaking complex SoC/IP subsystems, live in System Verilog/UVM, and can drive constrained-random verification like second nature, you’ll feel right at home.
Responsibility
- You’ll craft solid testbenches, nail coverage closure, debug without blinking, and handle protocols like AXI, AHB, APB, PCIe with ease. VCS, Questa, Xcelium, Verdi, Jenkins, Git, Python/TCL—if these are your everyday tools, let’s talk.
- If your CV shows UVM, SVA, functional coverage, strong scripting, and solid protocol depth, drop me a note.
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Design Verification Engineer
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