Memory Layout Engineer

3 weeks ago

PuneHyderabadDelhi NCR, IN SILCOSYS Solutions Pvt. Ltd Full time

Job Description :


- We are seeking a talented and motivated Memory Layout Engineer with 2 to 5 years of experience to join our dynamic team.

- The ideal candidate will have a strong background in memory layout design, including SRAM, DRAM, and ROM, with a focus on optimizing performance, area, and power.

- This role requires a comprehensive understanding of layout techniques, design rules, and verification processes to ensure the highest quality and reliability of our memory products.

Key Responsibilities :

- Layout Design : Design and implement layouts for various memory components (e.g., SRAM, DRAM, ROM) using advanced EDA tools.

- Collaboration : Work closely with circuit design engineers to understand specifications and translate them into efficient layout designs.

- EDA Tools Usage : Utilize industry-standard EDA tools such as Cadence Virtuoso, Synopsys Custom Compiler, or Mentor Graphics for layout design and verification.

- Design Rule Compliance : Ensure designs comply with foundry-specific design rules and constraints, including DRC (Design Rule Check) and LVS (Layout Versus Schematic) checks.

- Optimization : Optimize layouts for performance, area, and power, considering factors like matching, parasitic reduction, and signal integrity.

- Verification : Conduct thorough layout verification, including running DRC, LVS, and ERC (Electrical Rule Check) to ensure design accuracy.

- Documentation : Maintain comprehensive documentation of layout design processes, methodologies, and best practices.

- Tape-out : Prepare and execute tape-out procedures, ensuring that all design criteria and project timelines are met.

- Process Improvement : Contribute to the development and enhancement of layout design methodologies and flows.

Required Qualifications :

- Education : Bachelor's or Master's degree in Computer Science or a related field.

- Experience : 2 to 5 years of hands-on experience in memory layout design.

Technical Skills :

- Proficiency in using Cadence Virtuoso Layout Suite and other EDA tools.

- Strong understanding of memory technologies, including SRAM, DRAM, and ROM.

- Experience with full-custom layout of memory cells and arrays.

- Knowledge of parasitic extraction, matching techniques, and EM/IR analysis.

- Familiarity with DRC, LVS, and ERC verification tools and processes.

Soft Skills :

- Excellent problem-solving and analytical skills.

- Strong communication skills, both written and verbal.

- Ability to work independently and as part of a team.

- Detail-oriented with strong organizational skills.

(ref:hirist.tech)

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