FPGA Verification Engineer
2 days ago
Salary : 12-25 LPA
5+ years of experience with below skills :
- Hands on experience in developing SV UVM verification environment from scratch.
- Hands on experience with Questa or Modelsim or similar advanced simulation tools.
- Hands on experience in DO-254 verification process.
- Hands on experience in developing UVM verification environment from scratch from scratch with stimulus to achieve the code coverage, robust testing of the designs independently.
- Exposure to test plan generation, test bench writing, simulation of designs.
- Exposure to FPGA design/verification using VHDL will be a plus.
Responsibilities :
Verification Environment Development :
- Design and develop SystemVerilog UVM verification environments from scratch to test FPGA designs.
Simulation Tool Utilization :
- Utilize advanced simulation tools like Questa or Modelsim to perform simulations and validate designs.
DO-254 Compliance :
- Ensure that all verification activities comply with the DO-254 verification process, focusing on safety and reliability.
Test Plan and Test Bench Development :
- Generate detailed test plans and write test benches to simulate and verify FPGA designs.
Robust Testing :
- Develop stimuli to achieve comprehensive code coverage and conduct robust testing to identify and resolve design issues.
Documentation :
- Maintain clear and comprehensive documentation of verification processes, test plans, and results.
Collaboration :
- Work closely with FPGA designers and other team members to ensure thorough verification and validation of designs.
Continuous Improvement :
- Stay updated with the latest advancements in FPGA verification methodologies, tools, and industry standards to continuously improve the verification process.
(ref:hirist.tech)-
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