Static Timing Analysis Engineer

2 months ago


Bangalore, Karnataka, India Semi leaf Full time

We are hiring "STA experience 4+ years

Role : Individual contributor

Location : (Onsite -Bangalore)

Job Description :

- Deep understating and experience of STA tool PrimeTime /Tweaker/ DMSA(PTECO) .

- Knowledge of timing corners/modes, process variations and signal integrity related issues are required.

- Experience in timing closure of high frequency blocks & subsystems (Ghz range )

- Experience in working full-chip STA closure, defining mode requirements and corners for timing closure.

- Strong Understanding of DFT modes requirements for timing signoff

- Good understanding of physical design flow and ECO implementation.

- Strong understanding of SDC constraints, OCV, AOCV, POCV analysis.

- Strong TCL/scripting knowledge is mandatory.

- Strong Experience in Synthesis Constraints development, LINT checks, CDC checks

- Experience in Formal Verification with Synopsys Formality and / or Cadence Conformal LEC.

- Strong understanding of ECO cycle, should be able to generate and implement functional Ecos

- Strong TCL/scripting knowledge is mandatory.

- Understanding of timing constraints & physical design flow

Mandatory Skills :

- Deep understating and experience of STA tool PrimeTime /Tweaker/ DMSA(PTECO) .

- Knowledge of timing corners/modes, process variations and signal integrity related issues are required.

- Experience in timing closure of high frequency blocks & subsystems (Ghz range )

- Experience in working full-chip STA closure, defining mode requirements and corners for timing closure.

- Good understanding of timing constraints, physical design flow and ECO implementation.

- Strong understanding of SDC constraints, OCV, AOCV, POCV analysis.

- Strong TCL/scripting knowledge is mandatory.

Good to have Skills :

- Strong Experience in Synthesis Constraints development, LINT checks, CDC checks

- Experience in Formal Verification with Synopsys Formality and / or Cadence Conformal LEC.

- Strong Understanding of DFT modes requirements for timing signoff

(ref:hirist.tech)

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