ASIC RTL Engineer

Hi All,Greetings' from Eximietas Design.!We are Hiring ASIC SOC RTL Design Engineer/Leads.Job Title: ASIC SOC RTL Design Engineer/Leads..!Experience: 8+ Years.Location: Bengaluru or Visakhapatnam or San Jose, Bay Area, & Austin, USA.Anyone with a Valid H1B or Already in US.Job Description:Eximietas Design is seeking an experienced and highly skilled ASIC SOC...

Job Description:Own RTL design of SoC-level or large subsystems from specification to silicon bring-up.Define and implement micro-architecture; write high-quality, synthesizable RTL in SystemVerilog/Verilog.Work closely with physical design teams for synthesis, timing closure, power, area optimization, DFT hooks, and ECOs.Drive block/subsystem integration...

RTL, Coding, Design, IP Design, SOC Development, Lint, CDC , Micro Architecture  - Mandatory PCIe/DDR/Ethernet - Any OneI2C,UART/SPI  - Any One    Spyglass Lint/CDC / Synopsys DC / Verdi/Xcellium - Any OneScripting languages like Make flow, Perl ,shell, python - Any OneASIC RTL EngineerExpertise in SoC subsystem/IP designExpertise in IP design,...

Greetings of the dayThis is regarding a Job opportunity with eInfochips as we are having a position of ASIC RTL DESIGN ENGINEERSExperience- 5+ YearsLocation- Bangalore, AhmedabadJob Description:Experience in RTL designVerilog/VHDLSimulation tools, Modeslim/VCS etc.Basic protocols, I2C, UART, PCIe, SPI etc.Micro-Architecture experience is a plusCDC/Lint...

ASIC Design EngineerWe are seeking a skilled ASIC Design Engineer with a solid background in digital design, RTL coding, and ASIC development. The ideal candidate will have extensive experience in designing, developing, and optimizing high-performance ASICs, with a strong focus on SystemVerilog or VHDL. This role will involve taking designs from concept to...

4+ years of experience who will be responsible to taking ownership of our SPI interface and configuration register management.At least 2 Years/2 projects in ASIC RTL design. Pure FPGA RTL profiles will not be considered.The designer will take responsibility for modifying the existing IP to support a new command and data protocol. The previous IP supported...

The ASIC RTL Design Lead Engineer will lead the design and development of RTL for high-performance, low-power ASICs. The candidate will be responsible for architecting, designing, and implementing digital circuits using industry-standard RTL design methodologies. This individual will also manage a team of design engineers, provide technical leadership, and...

Senior RTL Design Engineer DSP / ASIC / FPGAExperience: 10 to 15 yearsLocation: Bangalore (On-site)Employment Type: Full-time / PermanentAbout the RoleWe are seeking a highly skilled Senior RTL Design Engineer to join our digital design team. The selected candidate will be responsible for the RTL design and development of signal processing pipelines for...

Minimum qualifications:Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.3 years of experience with Register-Transfer Level (RTL) design and integration using Verilog/System Verilog, microarchitecture and automation.3 years of experience with the Register-Transfer Level...

Minimum qualifications:Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.4 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog.3 years of experience in ASIC design flows and methodologies, IP...