Senior Lead

2 weeks ago

Greater Bengaluru Area, IN Tessolve Full time

Tessolve – Physical Design Engineer (5+ Years Experience)

Location: Bangalore

Job Type: Full-time

Experience: 5–10 years

Domain: ASIC / SoC Physical Design

Job Summary

We are looking for an experienced Physical Design Engineer with strong expertise in ASIC/SoC implementation flows including floor planning, synthesis, place & route, timing closure, and sign-off. The candidate should have hands-on experience working on advanced technology nodes (7nm/5nm/16nm) and delivering high-quality, tapeout-ready designs.

Key Responsibilities

Physical Design Implementation

  • Perform RTL-to-GDSII implementation including synthesis, floor planning, placement, CTS, routing, physical verification, and sign-off.
  • Develop and optimize block-level and/or top-level floorplans considering area, power, and performance targets.
  • Drive clock tree synthesis with skew, insertion delay, and power optimizations.
  • Execute place-and-route in Cadence Innovus / Synopsys ICC2 or equivalent tools.

Timing Closure & Power Optimization

  • Perform STA at block and top level using Synopsys PrimeTime.
  • Apply congestion fixes, ECOs, and timing optimizations (setup/hold/noise/DRC fixing).
  • Analyze and optimize IR drop, EM, power, and routing congestion.

Sign-off & Verification

  • Run and debug DRC/LVS checks using Mentor Calibre or Cadence Pegasus.
  • Support functional ECO and timing ECO implementation.
  • Manage sign-off flows including STA, SI/Noise, EM/IR, and DFT-aware implementation.

Cross-Functional Collaboration

  • Work closely with RTL, DFT, STA, and Packaging teams to achieve timing, area & power closure.
  • Participate in design reviews and methodology enhancements.

Required Skills & Experience

  • 5+ years of hands-on Physical Design experience in ASIC or SoC projects.
  • Strong expertise in:
  • Cadence Innovus / Synopsys ICC2
  • Synopsys PrimeTime
  • Calibre / Pegasus
  • RTL-to-GDS flow & sign-off methodologies
  • Experience with advanced nodes (16nm/12nm/7nm/5nm preferred).
  • Solid understanding of:
  • Clocking concepts & CTS
  • STA concepts (ON/OCV/AOCV/POCV)
  • IR drop, EM, and power optimization
  • Floorplanning, routing & physical verification
  • Experience with in-design physical verification flows is a plus.
  • Strong scripting skills in Tcl, Python, Perl, or Shell.

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