Design Verification Engineer

Job Description :- BE/BTech/ME/MTech - Electrical / Electronics / VLSI with an experience as a design and verification engineer.- At least 3 Years of relevant Industry experience - Strong background on functional verification fundamentals, environment planning, test plan generation, environment development is a must.- Design Verification experience verifying...

Job Description :- BE/BTech/ME/MTech - Electrical / Electronics / VLSI with an experience as a design and verification engineer.- At least 3 Years of relevant Industry experience - Strong background on functional verification fundamentals, environment planning, test plan generation, environment development is a must.- Design Verification experience verifying...

Position Title : Senior Engineer - ASIC Design Verification Location : Period : Immediate to 15 daysRole & Responsibilities :- An expert level with developing UVM-based SV test-benches.- Highly experienced with defining block, sub-system and SOC top level test plans.- Relevant experience with one or more of PCIe, NVMe, NAND, DDR and CPU sub-systems.- Deep...

Position Title : Senior Engineer - ASIC Design Verification Location : Period : Immediate to 15 daysRole & Responsibilities :- An expert level with developing UVM-based SV test-benches.- Highly experienced with defining block, sub-system and SOC top level test plans.- Relevant experience with one or more of PCIe, NVMe, NAND, DDR and CPU sub-systems.- Deep...

Job Description :We are seeking a skilled and dedicated Design Verification Engineer with 3 to 6 years of experience to join our innovative team. The ideal candidate will have a strong background in design verification methodologies and will be responsible for ensuring the quality and reliability of our ASIC and SoC designs.This role requires a comprehensive...

Job Description :We are seeking a skilled and dedicated Design Verification Engineer with 3 to 6 years of experience to join our innovative team. The ideal candidate will have a strong background in design verification methodologies and will be responsible for ensuring the quality and reliability of our ASIC and SoC designs.This role requires a comprehensive...

Job Description:We are seeking a skilled Physical Verification Engineer with 5 - 12 years of experience to join our team. The ideal candidate will have expertise in physical design implementation and signoff at the block level, particularly at 16/7nm technology nodes. Key responsibilities include floor planning, clock tree synthesis (CTS), static timing...

Job Description:We are seeking a skilled Physical Verification Engineer with 5 - 12 years of experience to join our team. The ideal candidate will have expertise in physical design implementation and signoff at the block level, particularly at 16/7nm technology nodes. Key responsibilities include floor planning, clock tree synthesis (CTS), static timing...

Job Description :1. Must Have: GLS or SoC or IP Verification2. Experience Languages: System Verilog3. Methodologies: OVM/UVM/VMM4. Protocols: PCIE/NVMe/DDR/Ethernet5. Candidate must have expertise in System Verilog.6. Experience in ARM base SoC Verification7. Strong Analytical skills are desirable if having worked8. Hands-on experience on Assertions and...

Job Description :1. Must Have: GLS or SoC or IP Verification2. Experience Languages: System Verilog3. Methodologies: OVM/UVM/VMM4. Protocols: PCIE/NVMe/DDR/Ethernet5. Candidate must have expertise in System Verilog.6. Experience in ARM base SoC Verification7. Strong Analytical skills are desirable if having worked8. Hands-on experience on Assertions and...

About the job:Job Location: Bangalore/ Hyderabad/Pune and NoidaNotice Period: 15 days to 30 DaysMinimum: 4 YearsKey Responsibilities:- Developing test plans- Coding and bring up of asm, c++ tests- UVM test bench components coding and maintaining- Debugging regression fails- Protocol: DDR,PCIE,USB,MIPIPreferred Experience:- Should have worked on Processor...

About the job:Job Location: Bangalore/ Hyderabad/Pune and NoidaNotice Period: 15 days to 30 DaysMinimum: 4 YearsKey Responsibilities:- Developing test plans- Coding and bring up of asm, c++ tests- UVM test bench components coding and maintaining- Debugging regression fails- Protocol: DDR,PCIE,USB,MIPIPreferred Experience:- Should have worked on Processor...

We are seeking a highly skilled Senior Static Timing Analysis (STA) Engineer with 5-10 years of experience in digital ASIC design and timing closure. As a Senior STA Engineer, you will play a key role in ensuring the timing integrity and performance of our advanced semiconductor designs.Key Responsibilities :- Perform comprehensive static timing analysis...

We are seeking a highly skilled Senior Static Timing Analysis (STA) Engineer with 5-10 years of experience in digital ASIC design and timing closure. As a Senior STA Engineer, you will play a key role in ensuring the timing integrity and performance of our advanced semiconductor designs.Key Responsibilities :- Perform comprehensive static timing analysis...

We are hiring for the Physical Design Engineer / Leads role.JOB Designation : Physical Design Engineer / Leads.JOB Location : Bangalore, Hyderabad, Chennai, Noida, Pune, Ahmedabad. Mode of Hiring : Full-time [FTE], Onsite, 5 Days. Notice Period : Immediate to 15 days. Experience : 4-12 years. Required Skills :- Depth experience in Physical Design...

We are hiring for the Physical Design Engineer / Leads role.JOB Designation : Physical Design Engineer / Leads.JOB Location : Bangalore, Hyderabad, Chennai, Noida, Pune, Ahmedabad. Mode of Hiring : Full-time [FTE], Onsite, 5 Days. Notice Period : Immediate to 15 days. Experience : 4-12 years. Required Skills :- Depth experience in Physical Design...

Role : DFT Engineer. Location : Pan India. Main Skills : DFT, RTL, Verification. Experience : 4+ Years.Payroll : Spruce IT Pvt Ltd. Notice Period : Immediate to 30 Days. Job Description :- Implementation tools like Mentor Tessent Fastscan, Testkompress or Synopsys DFT compiler and Tetramax.- Sound knowledge of ATPG/Scan, coverage analysis, EDT compression...

Role : DFT Engineer. Location : Pan India. Main Skills : DFT, RTL, Verification. Experience : 4+ Years.Payroll : Spruce IT Pvt Ltd. Notice Period : Immediate to 30 Days. Job Description :- Implementation tools like Mentor Tessent Fastscan, Testkompress or Synopsys DFT compiler and Tetramax.- Sound knowledge of ATPG/Scan, coverage analysis, EDT compression...

Profile : VLSI Design EngineerOpen for PAN IndiaJunior and Senior RoleJob description :- Responsible for the design and development of the electronics for Maticas card printers and related products, including generating formal specifications, verification tests and production documentation for release- Responsible for RTL design, SoC integration and work...

We are seeking an experienced Senior Design for Test (DFT) Engineer to join our dynamic team. The ideal candidate will have 5-10 years of proven industry experience in DFT methodologies and techniques. As a Senior DFT Engineer, you will be responsible for developing and implementing DFT strategies to ensure the highest quality and testability of our...