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Physical Design Engineer

4 months ago

Bangalore, Karnataka, India Symphony HR Full time

Hiring for Bengaluru at multiple levels - 6 to 20 years of experience in physical design, VLSI, Floor planning, power planning, SOC, PNR Looking for Familiar with handling block/SOC level RTL (Register Transfer Level) to GDS2 (final layout)

- Knowledgeable about low power checks and processes, including MVRC/CLP, LEC/Formality, DRC, LVS, IR, EM

- Experience in low-power design techniques with experience with 10nm, 7nm, and 5nm technology nodes

- Experience with Synopsys and Cadence tools

- Floor Planning & Power Planning and Clock Tree Synthesis

- Deep understanding and experience with all physical design activities for large SOC ASIC chips

- Extensive experience with various Place and Route (PNR) tools like Synopsys ICC2, ICC, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk

- Experience in full-chip floorplanning and PNR partitioning/bump placement is preferred

- Experience in designing for low power and high performance

- Self-driven with strong problem-solving skills and a drive for improvements

- Excellent communication skills (both written and oral)

(ref:hirist.tech)