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Rtl Design Lead
1 week ago
As a global semiconductor company, we design, manufacture, test and sell analog and embedded processing chips to nearly 100,000 customers.
Our products enable electronics everywhere and in things you experience every day - from health care, smart homes and connected cars to drones, smart phones and more.
Our passion to create a better and more sustainable world by making electronics more affordable through semiconductors drives us to make our technology smaller, more efficient, more reliable and more affordable.
ABOUT The Team:
The Sitara MPU product line is a rapidly expanding business within TI, investing to address the fast-growing segment of high-performance processors in industrial & automotive markets
This product line will enable a scalable portfolio of ARM based high-end MPUs as emerging trends in AI & analytics, motor control, robotics, HMI and real-time networking are shaping the evolving requirements for applications like autonomous robots, renewable energy, factory and home automation.
The newly formed Sitara MPU team in India will focus on expanding the breadth of TI's portfolio by scaling the execution of MPU devices in 16 FF node and is looking for passionate leaders who can partner to make this a realityResponsibilities :
Lead So C FE team to own So C integration of a complex ARM architecture based So C upto RTM
Manage a high impact FE team and take accountability for their timely deliverables
Interact and engage early-on with So C system architect and ensure performance analysis, functional safety requirements, system level use-cases and pin mixing is fully comprehended
Drive complete So C integration, LEC, LINT checks and CDC/RDC analysis to ensure high quality deliverables
Responsible for ensuring power intent of the So C is understood and implemented correctly through Low-Power checks like CLP
Ownership of power estimation through the cycle and responsible for meeting/beating active and leakage power targets for the device in different modes
Collaborate with systems, IP and DV teams to align on feature updates, bug fixes, IP deliverables and ensure timely So C integration releases that cater to Product Requirements
Skills :
Experience with integration of So C's with ARM processors, complex bus architectures
Well experienced with analysis and understanding of system level use case scenarios, safety requirements etc
Experience with So C power analysis and power optimization through innovative schemes
Strong experience with advanced low power techniques and tools such as UPF/CPF, CLP
Good understanding of constraints development for Physical Design implementation / Static Timing Analysis
Experience with industry standard Front End tools like Jasper Gold, Spy Glass, LEC etc
Well experienced with EDA tools such as VCS/Questa/Incisive simulators, Debug tools and Formal verification tools
Good understanding of So C Debug architectures, Design-for-Debug, Design-for-Test will be highly desirable
Strong written and verbal communication skill with the ability to explain and present complex ideas
Passionate about mentoring and developing people in their careers
Qualifications
Minimum requirements:
Educational requirement Bachelor or Masters in EE/ECE/CS or related specializations
9+ years of experience in IP/So C/subsystem design/integration
Why TI?
Engineer your future.
We empower our employees to truly own their career and development.
Come collaborate with some of the smartest people in the world to shape the future of electronics.
We're different by design.
Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger.
We value each and every voice, and look forward to hearing yours.
Meet the people of TI
Benefits that benefit you.
We offer competitive pay and benefits designed to help you and your family live your best life.
Your well-being is important to us.
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