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Senior Design Engineer

3 months ago

Bengaluru, Karnataka, India 7Rays Semiconductors India Private Limited Full time

About Company

At 7Rays Semiconductors ), we provide end-to-end VLSI design solutions to help our clients achieve execution excellence. Our team of experts specializes in architecture, RTL design, verification, validation, physical design, implementation, and post-silicon validation using the latest technologies and methodologies

We work closely with our clients, building effective partnerships to deliver high-quality solutions tailored to their needs. With a proven track record of successful projects, we are committed to excellence and innovation in semiconductor design.

Senior DFT Engineer

Bangalore, India

Experience level 4-10 Years (DFT Lead)

Role -

  • The candidate is expected to have clear understanding of BSCAN,MBIST, SCAN, ATPG and Simulation concepts.
  • Must be hands-on with MBIST insertion, Scan Insertion, ATPG pattern generation and simulations, MBIST and BSCAN simulations using industry standard tools of Cadence/Siemens Tessent/Synopsys.
  • He/she must have worked on zero delay as well as SDF Timing Simulations.
  • Must have good debugging skills using GUI mode of industry standard simulators like VCS, NCSim or Xcelium.
  • The candidate should have worked on fault models like stuck-at, Transition Delay Faults(TDF), IDDQ and should have experience in scan test coverage improvement techniques.
  • He/she should have worked in SoC level DFT with experience in OCC/OPCG insertion, EDT/Compression logic insertion, clock module handling for scan purposes and post-silicon bring-up and /or production activities with exposure to Tester debug usings shmoo plots and graphs.
  • The candidate should have experience of providing test mode timing constraints to STA and PD teams.
  • Additional knowledge of perl/tcl scripting will be an advantage.
  • Good communication skills and debugging skills are a must to have qualities for this role as it involves cross-functional teams and customer teams communications along with internal DFT team leading and mentoring of DFT Engineers.