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Analog Layout Engineer
3 months ago
• Contribute to area estimation and optimization, floor planning, power routing, shielding, physical verification (DRC, ERC, LVS, ESD, , as well power analysis (EM / IR-Drop)
• Contribute and support team in taping out high-performance microcontroller chip.
• Actively seek out opportunities to work with cross-functional teams (Chip team, Tech, CAD)
• Develop scripts and methods for layout design automation.
Requirements:
· BS/ in Electrical Engineering or related field + 8 years of experience, or MS/ + 6 years of experience preferred with experience in analog/mixed-signal layout design of deep submicron CMOS and BCD technologies.
· Experience in delivering high quality analog layout IPs.
· Good understanding of layout fundamentals and best practices
· Proficiency in interpretation of CALIBRE DRC, ERC, LVS, reports
· Programming knowledge in SKILL, Perl, and/or Python is a bonus.
· Experience with CADENCE or MENTOR GRAPHICS layout tools
· Solid understanding of semiconductor manufacturing process and DFM techniques
· Proficient at debugging/fixing LVS/DRC errors.
· Must be familiar with Cadence Design Environment (CDE) and Unix OS
· Must have strong communication skills and be a team player.