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Senior Physical Design Engineer
2 weeks ago
- Fusion compiler / Cadence flow (Innovus)
- Good understanding Macro placement, Floorplanning, placement CTS, Routing
- Design planning ( partitioning, bump planning & Routing )
- Very good understanding of STA
- Very good Debugging skill
- Handling atleast 10 member team and driving project
- Understanding about Analog block integration
- Power grid creation
- Low power design>> Signoff checks
- LEC ( conformal )
- RV ( ansys )
- LV ( drc clean up – caliber )
- PTPX
- VCLP ( vc static checks )
- Caliberlite ( intel internal )
- Timing closure ( PT ECO/ Tweaker )
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