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Design Verification Engineer
3 months ago
Are you a seasoned professional with over 3 years of experience in ASIC/FPGA verification? We're looking for a dynamic and skilled individual to join our team
Key Qualifications:
- Proven expertise in System Verilog and a MUSThave proficiency in UVM.
- Extensive handson experience in IP/Subsystem/SOC Verification.
- Track record in coveragedriven verification methodologies.
- Strong proficiency in creating and maintaining testbenches (stimulus, agent, monitor, checker).
- Proficient in failure debugging using industrystandard tools such as Verdi, DVE, Simvision, and log file analysis.
- Solid background in SOC verification with C/ASMbased test development.
- Expertise in assertion development.
- Familiarity with EDA tools like IUS, VCS, Questasim, etc.
- Proficiency in scripting languages such as Perl and Python.
- A collaborative team player with excellent communication skills, capable of proactive interaction with designers and fellow verification engineers.
Additional Experience:
- Exposure to various verification tasks, including gatelevel simulation, poweraware simulation, formal verification, subsystem verification, and emulation.
- Knowledge of AMBA protocols, High-Speed and Low-Speed peripherals, Memory interface protocols, image processing, etc.
- If you're passionate about pushing the boundaries of verification in a collaborative environment, this is the perfect opportunity for you Join us in creating cuttingedge solutions and contribute to the success of our innovative projects.
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